Hmos 1978 Step 13 Quantify Static Power Dissipation

# Step 13 — Quantify HMOS's Own Static Power Dissipation, the Cost CMOS Would Later Remove

## 1. Isolate the Term the Depletion-Load Inverter Can Never Turn Off

Step 1 wrote dynamic power as $P\approx C V_{dd}^2 f$ and treated it as the term HMOS's process engineering could chip away at — thinner oxide, shorter channel, silicide shunts. That equation is incomplete for a ratioed NMOS inverter. Whenever a depletion-load inverter's output sits at a LOW logic level, its enhancement-mode pull-down transistor is ON and its depletion-mode load is also ON, and current flows continuously from the supply to ground through both of them for as long as that output stays LOW — not just during a transition. This is static power, and unlike dynamic power it does not depend on clock frequency at all; it depends only on how many of a chip's gates are sitting at a LOW output at any given instant and how that number scales with transistor count.

$$P_{static}=I_{DD}V_{dd}$$

where $I_{DD}$ is the DC current a single ratioed inverter draws while LOW, set by the aspect-ratio sizing Step 3 of the base series worked out for the current-matching tradeoff. That sizing decision was made to balance switching speed and noise margin; it was never aimed at minimizing $I_{DD}$, because in a single-inverter design $I_{DD}$ is a small, tolerable number. The problem is what happens when that small number is multiplied by tens of thousands of gates on a single die.

Static Current Flows Continuously Through Every LOW Gate a depletion-load inverter holding a LOW output, not a switching transient DEPLETION LOAD always ON (pull-up) ENHANCEMENT PULL-DOWN ON (output held LOW) I_DD flows supply → ground continuously, not briefly one gate: small, tolerable I_DD tens of thousands of gates: aggregate climbs WHAT STEP 3'S SIZING DECISION NEVER OPTIMIZED aspect-ratio sizing in Step 3 balanced switching speed against noise margin, on the assumption that one inverter's I_DD was a small, tolerable number that assumption breaks down at the gate counts a flagship microprocessor integrates

## 2. Put a Number on It at HMOS's Own Integration Density

A representative ratioed NMOS inverter of this era draws DC current on the order of hundreds of microamps while held LOW, depending on the exact aspect ratio chosen. An HMOS microprocessor integrating on the order of twenty-nine thousand transistors — roughly the 8086's published count — does not have every gate held LOW simultaneously, but a fixed, architecture-dependent fraction of them are LOW at any instant in normal operation, and that fraction's aggregate current does not go to zero the way dynamic switching current does between clock edges. Multiplying a representative per-gate static current by a representative fraction of simultaneously-LOW gates at this transistor count produces an aggregate static power draw measured in the hundreds of milliwatts to single-digit watts range at a 5 V rail — a genuinely significant fraction of the chip's total power budget, present whether the clock is toggling or sitting idle.

This is HMOS's own limitation, not a defect introduced by any individual process choice in Steps 2 through 6. It is structural to the ratioed-inverter topology itself: no amount of oxide thinning, channel shortening, or silicide shunting removes a current path that exists because the pull-up device is never off. The base series' own Step 9 already flagged that CMOS's complementary pull-up/pull-down pair eliminates exactly this term by construction, since in steady state one of the two complementary devices is always off; this step is what makes that comparison concrete rather than qualitative, by putting HMOS's own static number on the table before any CMOS comparison is made.

Static Power as a Fraction of HMOS's Total Power Budget present regardless of clock state — this is the term Step 9 said CMOS removes by construction STATIC TERM, I_DD V_dd ~hundreds of µA per gate held LOW × fraction of ~29k transistors LOW × 5 V rail ~hundreds of mW to low single-digit W present whether clock toggles or idles no process fix in Steps 2-6 removes it DYNAMIC TERM, C V_dd² f shrinks with every process refinement Steps 2-6 attacked this term directly zero when the clock is idle genuinely reducible by process work HMOS'S OWN HONEST LIMIT every improvement Steps 2-8 engineered attacked the dynamic term; the static term never moved this is the number the parallel CMOS-power-crossover series (cmoscrossover-1980) resolves against, not here

## 3. Place This Step in the Extension's Own Lineage

This step puts a concrete number on a cost the base series' Step 9 only named qualitatively, and it sets up, without resolving, the question the separately-deployed `cmoscrossover_1980` series answers at length: at what integration density does this static term stop being a tolerable fraction of total power and start deciding the architecture decision outright. That resolution belongs to that series, not to this one; here the point is narrower — HMOS's static power is structural to its own topology, present from the first device Step 2 of the base series built, and no amount of the process engineering documented across this entire extension removes it. Step 14 turns to a second structural cost of HMOS's own higher internal fields: hot-carrier degradation at a severity specific to HMOS's thinned oxide and shortened channel, distinct from the generic treatment given to the broader 1970s NMOS lineage elsewhere in this project.

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