Hmos 1978 Depletion Load Redesign Shorter Channel Without Raising Field

# Redesign the Load Device So a Shorter Channel Does Not Mean a Higher Field

## 1. Isolate the One Device That Was Never the Bottleneck Until Now

Standard enhancement-mode NMOS logic pairs a fast switching transistor with a second device, the depletion-mode load, whose job is simply to pull the output node back up once the switching transistor turns off. Through the 1960s and early 1970s this load device was treated as a fixed, unglamorous supporting part — its channel doping set once, at a length generous enough to behave predictably, and left alone while all of the design attention went to the switching transistor Step 1 showed under field stress.

HMOS inverts that priority. Intel's High-performance MOS process re-examines the depletion load specifically because the switching transistor's own geometry can no longer be shrunk the naive way — Step 1 established that cutting its channel length $L$ at fixed $V_{dd}$ drives $E=V/L$ upward with every generation. HMOS's answer is not to abandon scaling. It is to buy back headroom in $E$ by changing *how* the channel is formed, so a shorter physical $L$ no longer forces a proportionally higher field, and then to redesign the depletion load so it can keep pace with a switching transistor that is now faster, smaller, and differently doped than the device it replaces.

The Depletion Load Moves From Fixed Part to Co-Designed Device once the switching transistor's geometry changes, the load device can no longer be left alone CONVENTIONAL NMOS (PRE-HMOS) switching transistor: attention and tuning depletion load: fixed doping, generous L treated as a supporting part, left alone across generations works only while the switcher scales slowly HMOS switching transistor: shorter L, re-engineered depletion load: redesigned to match both devices co-designed against the same field budget load keeps pace with a faster switcher THE LOAD DEVICE WAS NEVER THE BOTTLENECK UNTIL THE SWITCHER MOVED scaling one half of the inverter pair forces a redesign of the half left behind the mechanism: ion implantation sets load doping independently from the switching transistor's own channel process — Section 2

## 2. Use Ion Implantation to Decouple the Load's Doping From the Switcher's

The mechanism that makes co-design possible is ion implantation of the depletion load's channel. Rather than relying on the same diffusion step that sets the switching transistor's threshold, HMOS implants a separate, precisely controlled dose of dopant directly into the load device's channel region, setting its threshold voltage $V_{t,load}$ independently of whatever process change the switching transistor just underwent.

This decoupling matters because the two devices now have conflicting requirements that a single shared process step could never satisfy simultaneously. The switching transistor wants the shortest channel its field budget allows, to maximize speed. The load device wants a threshold and channel length tuned to supply exactly enough pull-up current to restore the output node within one clock period — no more, because excess pull-up current fights the switching transistor during its own conduction phase and wastes power, and no less, because insufficient pull-up current is simply a slower gate. Ion implantation gives HMOS a free parameter — implant dose — that tunes $V_{t,load}$ without touching the switching transistor's own doping profile at all:

$$V_{t,load}=V_{t0}-\frac{qN_{implant}}{C_{ox}}$$

A shallow, well-controlled implant dose $N_{implant}$ shifts the load's threshold by a known, reproducible amount, independent of the main channel process. This is the same physical tool — controlled dopant placement separate from the device's primary formation step — that the 1970s ion-implantation series established for threshold control generally; HMOS is that tool's application to the specific problem of keeping two devices in one inverter pair in balance while only one of them is shrinking.

Implant Dose Becomes an Independent Tuning Knob Real Diagram — the HMOS inverter pair, each device set by its own process step OUTPUT NODE must be pulled up by the load, pulled down by the switcher DEPLETION LOAD Vt,load set by implant dose N independent of switcher process Vt,load = Vt0 − qN/Cox tuned for exactly enough pull-up SWITCHING TRANSISTOR shortest L the field budget allows own doping, own oxide, Step 1's E optimized purely for speed no longer constrained by load's needs balanced pair TWO DEVICES, TWO INDEPENDENT PROCESS STEPS, ONE BALANCED INVERTER implantation is what makes "co-designed" an achievable instruction rather than a wish net result: faster switching, controlled pull-up, same E budget — Section 3

## 3. Connect the Payoff Back to Step 1's Field Budget, and Forward to the Project's Own Implant Lineage

The payoff of this redesign is not that HMOS escapes the field relationship Step 1 derived — $E=V/L$ still governs the switching transistor exactly as before. The payoff is that HMOS no longer needs the depletion load's design to silently absorb a mismatch the switching transistor's own scaling created. Before this redesign, a shrunk switching transistor paired with an unchanged load device would either starve for pull-up current (too slow) or fight itself every cycle (wasted power) — a second-order failure layered on top of the field problem Step 1 already identified. Implantation removes that second-order failure as a design concern, leaving engineers free to push the switching transistor's own field-constrained scaling as far as Step 1's budget allows, confident that the load device will track it.

This step also draws the clearest possible line back into this project's own lineage. The 1970s ion-implantation series established implantation as this project's general tool for setting a threshold voltage precisely, independent of the diffusion steps used to build the rest of the device — at the time, that series framed the tool mainly around single-transistor threshold control. HMOS is the first point in this project's history where that same tool is applied *relationally*: not to tune one device in isolation, but to keep two devices in a matched pair synchronized while only one of them is undergoing aggressive geometric scaling. The next step examines what measuring that synchronization costs and buys — the aspect-ratio and current-matching tradeoffs HMOS designers had to quantify directly.

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