Hmos 1978 Quantify Current Matching and Aspect Ratio Tradeoff

# Step 3 — Quantify the Current-Matching and Aspect-Ratio Tradeoff

## 1. The Inverter Voltage Transfer Constraint: Securing $V_{OL}$

In a depletion-load NMOS inverter, output logic levels and noise margins are determined not by complementary switching, but by a ratioed current fight between pull-down and pull-up transistors. In Step 1, we established that keeping supply voltage fixed at $V_{dd} = 5.0\ \text{V}$ while shrinking channel length escalates the internal electric field $E = V/L$. In Step 2, we showed how ion implantation decouples the depletion load’s threshold $V_{TD}$ from the enhancement switcher’s threshold $V_{TE}$. But making this co-scaled inverter functional requires balancing their drive currents across switching transitions.

Unlike CMOS—where either the PMOS or the NMOS transistor is completely turned off in steady state—an NMOS inverter with a depletion-mode load ($V_{GS,L} = 0$) operates as an active current source fighting an active pull-down switch. When the input voltage is high ($V_{in} = V_{OH} = 5.0\ \text{V}$), the pull-down transistor $Q_D$ turns ON to pull the output to logic low ($V_{out} = V_{OL}$). To maintain a valid TTL-compatible low level and a sufficient low noise margin ($NM_L = V_{IL} - V_{OL}$), the design must enforce:

At this steady-state low operating point:
* The pull-down enhancement device $Q_D$ operates in its linear (triode) region because $V_{DS,D} = V_{OL} = 0.4\ \text{V} \ll (V_{in} - V_{TE})$:

* The pull-up depletion load $Q_L$ has $V_{DS,L} = V_{dd} - V_{OL} \approx 4.6\ \text{V} > |V_{TD}|$. Thus, $Q_L$ operates in saturation, delivering its full saturation current:

where $\beta = \mu C_{ox} (W/L)$ represents the transconductance parameter of each transistor.

## 2. The Aspect Ratio Tradeoff: Pre-HMOS Serpentine Loads vs. HMOS Sizing

Equating pull-down linear current to pull-up saturation current yields the required aspect ratio $K_R$:

For typical operating parameters ($V_{dd} = 5.0\ \text{V}$, $V_{TE} = 0.8\ \text{V}$, $V_{TD} = -2.5\ \text{V}$, $V_{OL} = 0.35\ \text{V}$), this ratio simplifies to:

When taking into account the body effect (as $V_{out}$ approaches $V_{OL}$, the depletion load’s source-to-substrate reverse bias shifts $V_{TD}$ via $\Delta V_T = \gamma(\sqrt{2\phi_F + V_{out}} - \sqrt{2\phi_F})$), the required aspect ratio climbs to $K_R \approx 3.5\text{ to }4.0$.

## 3. Place This Step in the Project's Own Lineage

Step 3 provides the quantitative circuit bridge that links process physics to microarchitecture:
1. The Ratioed Sizing Cost Unveiled: Step 1 showed why constant-voltage scaling pushed fields to dangerous levels, and Step 2 introduced ion implantation as the process lever to decouple threshold voltages. Step 3 delivers the circuit-level proof: without independent implant control of $V_{TD}$, maintaining $V_{OL} \le 0.4\ \text{V}$ required a $4:1$ aspect-ratio mismatch ($K_R \ge 4$), forcing fabs to lay out massive $L_L = 24\ \mu\text{m}$ load resistors that squandered die area.
2. The Density Dividend: By precisely adjusting the depletion implant dose ($D \approx 1\times 10^{12}\ \text{cm}^{-2}$), HMOS designers locked $V_{TD}$ at $-2.5\ \text{V}$. This allowed the load channel length to shrink from $24\ \mu\text{m}$ to $7\ \mu\text{m}$, slashing the inverter pair’s silicon area by $4\times$ while halving switching propagation delay ($t_{PLH}$).
3. Setting Up Gate Oxide Thinning: Having reclaimed layout density and current matching through aspect-ratio optimization, circuit designers faced their next performance bottleneck: drive current ($I_{on} \propto C_{ox} (W/L)$). In Step 4, we examine HMOS’s second scaling lever: thinning the gate oxide ($t_{ox}$) from $100\ \text{nm}$ down to $70\ \text{nm}$ to boost drive current without shrinking $L$ further, and confronting the resulting dielectric breakdown limits.