Hmos 1978 Compare Nmos Scaling Path Against Parallel CMOS Path

# Step 9 — Compare the NMOS Scaling Path Against the Parallel CMOS Path It Was Competing With

## 1. Why NMOS Dominated the 1970s: The Density and Cost Equation

Despite CMOS’s inherent zero-static-power advantage, NMOS dominated the microprocessor and memory revolution of the 1970s because it delivered more than double the circuit density at substantially lower manufacturing cost. In Step 8, we saw how the fixed-voltage NMOS scaling path eventually hit a wall in HMOS-II ($2.0\ \mu\text{m}$), where velocity saturation, hot carriers, and static DC power dissipation brought the paradigm to its end. But this raises a historical question: *Complementary MOS (CMOS) had been patented and demonstrated in 1963 by Frank Wanlass and Chih-Tang Sah at Fairchild. Why did the computing revolution of the 1970s—from the Intel 8080 and 8086 to the MOS 6502 and Zilog Z80—rely almost exclusively on NMOS?*

The answer lies in the harsh physical and economic balance sheet of 1970s semiconductor manufacturing:

1. The Well-Spacing and Mobility Area Penalty:
* In CMOS, both N-channel and P-channel transistors must coexist on the same substrate, requiring deep P-wells (or N-wells) diffused into the silicon. To prevent parasitic p-n-p-n thyristor triggering (latchup), design rules mandated massive well-to-active clearances of $10\text{ to }15\ \mu\text{m}$.
* Furthermore, hole mobility in silicon is significantly lower than electron mobility ($\mu_p \approx 220\ \text{cm}^2/\text{V}\cdot\text{s}$ vs. $\mu_n \approx 650\ \text{cm}^2/\text{V}\cdot\text{s}$). To balance inverter rise and fall times ($t_r \approx t_f$), the PMOS pull-up transistor had to be drawn $2.5\times\text{ to }3\times$ wider than the NMOS pull-down switch ($W_P \approx 2.5 W_N$).
* As a result, a 1978 CMOS inverter pair occupied $2.4\times$ the silicon area of an HMOS depletion-load inverter pair ($200\ \mu\text{m}^2$ vs. $85\ \mu\text{m}^2$).
2. The Mask-Count and Die-Cost Disparity:
* Standard single-poly NMOS required only 6 photolithography masks, and high-performance HMOS required 9 masks.
* A comparable 1978 silicon-gate CMOS process required 12 to 14 masks—demanding separate P-well diffusion, complementary source/drain $P^+$ and $N^+$ implants, well taps, and substrate contact masks.
* Fabricating a 29,000-transistor microprocessor like the Intel 8086 in CMOS would have required a die larger than $75\ \text{mm}^2$ (compared to HMOS’s $33\ \text{mm}^2$). On a 3-inch or 4-inch wafer, yield drops exponentially with die area ($Y \propto e^{-D \cdot A}$), making a 1978 CMOS 16-bit processor commercially unviable.

1978 Layout Density: HMOS Inverter vs. CMOS Inverter why NMOS delivered 2.4× greater density: well-isolation clearances and hole-mobility matching 1978 HMOS INVERTER PAIR (~85 µm²) QD Switch W=7 µm QL Load L=7 µm Poly 2 Total Cell Width: ~18 µm Cell Height: ~4.7 µm → Area = 85 µm² HMOS Advantages in 1978: • Single substrate doping (P-type bulk, no wells required) • 9 masks vs. 13 masks → 40% lower wafer fabrication cost ✓ 8086 fit on a 33 mm² die with 45% production yield 1978 CMOS INVERTER PAIR (~205 µm²) P-Well NMOS 12 µm Clearance (Latchup Margin) PMOS WP = 18 µm (μp ≈ μn / 2.5) Tap CMOS Penalties in 1978: • Well isolation + wide PMOS swelled inverter footprint by 2.4× • 13 masks required; wafer defect density 1.8× higher • 8086 in CMOS would have required > 75 mm² die (zero profit yield) THE ECONOMIC EQUATION OF THE 1970S ✓ 2.4× Density Advantage: NMOS fit more transistors onto affordable dice, launching the personal computer industry ✓ Process Simplicity: 9 masks vs. 13 masks gave NMOS a decisive margin in fab yield and unit production cost As long as chip power stayed under 2.5W, NMOS was the undisputed commercial champion.

## 2. What Flipped the Balance: The 1982–1985 Crossover Point

The balance flipped when VLSI transistor counts surged from 30,000 to over 100,000. In ratioed NMOS, static power grows monotonically with gate count:

$$P_{\text{NMOS}} \approx N_{\text{gates}} \cdot \left(\frac{1}{2} I_{\text{load}} V_{dd}\right)$$

In CMOS, static DC power is negligible ($P_{DC} \approx 0$). Power is consumed almost exclusively during dynamic switching:

$$P_{\text{CMOS}} \approx \alpha \cdot C_{\text{tot}} V_{dd}^2 f$$

Because typical microprocessor logic has an activity factor of only $\alpha \approx 0.10\text{ to }0.15$ (only 10–15% of nodes switch on any given clock edge), a 100,000-transistor CMOS processor dissipates $5\times\text{ to }10\times$ less power than an equivalent NMOS processor.

Simultaneously, sub-2-micron lithography, twin-well (twin-tub) processing, and shallow trench isolation reduced CMOS well-spacing design rules from $12\ \mu\text{m}$ down to $2\ \mu\text{m}$, collapsing the CMOS area penalty from $2.4\times$ to less than $1.25\times$.

The Historical Crossover: NMOS vs. CMOS (1974 → 1986) the economic and thermal inversion that dethroned NMOS and established CMOS as the VLSI standard TOTAL CHIP POWER DISSIPATION CROSSOVER Year / Transistor Count Power (W) 1974 (5k) 1978 (29k) 1982 (130k) 1985 (275k) NMOS (> 12W Meltdown) CMOS (1.5W – 2.5W) CROSSOVER 1982 – 1984 The Historic Turning Point: • Below 50,000 transistors: NMOS cost & density advantage was decisive ✓ Above 100,000 transistors: CMOS power savings made the extra masks essential THE INTEL PIVOT: HMOS → CHMOS Intel 80286 (1982, HMOS-III): • 134,000 transistors on NMOS • Power: 3.3 W (required heat sink) Intel 80386 (1985, CHMOS-III): • 275,000 transistors on 1.5 µm CMOS • Power: 1.8 W at 16 MHz! ✓ Standard plastic packaging maintained CHMOS: "Complementary HMOS" Retained HMOS implants inside CMOS twin-wells. The Architectural Continuity: NMOS did not fail—it paved the way. By funding tool development, ion implantation, thin oxides, and silicides, HMOS built the technical infrastructure that made modern sub-micron CMOS possible.

## 3. Place This Step in the Project's Own Lineage

Step 9 integrates the 1978 HMOS scaling path directly with the broader historical roadmap of semiconductor physics:
1. The 1963–1978 Bifurcation Explained: In the 1962–1963 series, we documented Wanlass and Sah’s discovery of complementary MOS. Step 9 explains why that breakthrough remained a niche technology for fifteen years: well clearances and hole-mobility mismatch made 1970s CMOS more than twice as large as NMOS, making NMOS the only economically viable path to build the first commercial microprocessors.
2. The Thermal Inversion Mechanism: As integration scaled past 50,000 transistors, the constant static DC power of ratioed NMOS logic collided with DIP packaging thermal dissipation limits ($2.5\ \text{W}$). CMOS’s near-zero static dissipation transformed from an expensive luxury into an absolute survival requirement.
3. Leading to the Series Retrospective: Having established why HMOS reigned supreme in the late 1970s and what necessitated its handover to CMOS, we conclude in Step 10 with the series retrospective: classifying what modern microprocessor architectures inherited from HMOS and what was abandoned as NMOS reached the end of its line.

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