CMOS Crossover 1980 Complete CMOS Versus Hmos Power Delay Comparison

# Pay Every Cost Back Into the Comparison That Started This Series

## 1. Rebuild Step 1's Comparison With Every Term This Series Has Since Added

Step 1 opened this series with a simplified comparison: $P_{total,NMOS}=I_{DD}V_{dd}+C_NV_{dd}^2f$ against $P_{total,CMOS}\approx C_CV_{dd}^2f$, and argued that at 1980s density, aggregate $I_{DD}V_{dd}$ had grown large enough to decide the outcome in CMOS's favor. That comparison was correct as far as it went, but it was also incomplete in exactly the way this series' own Steps 2 through 5 have since shown: CMOS's $P_{dynamic}$-only total is not actually free of further terms once guard rings and decoupling capacitance are accounted for. The honest comparison this step performs is not NMOS versus an idealized CMOS. It is HMOS versus the CMOS this series has actually built, cost by cost.

$$P_{total,HMOS}=I_{DD}V_{dd}+C_{HMOS}V_{dd}^2f_{HMOS}$$
$$P_{total,CMOS}=C_{CMOS}V_{dd}^2f_{CMOS}+P_{decap,leakage}$$
$$A_{total,CMOS}=A_{active}+A_{guardring}+A_{decap}$$

Every term on the right of the CMOS equations was introduced somewhere in Steps 2 through 5 of this series: $A_{guardring}$ from Step 3's perimeter-scaling rule, $A_{decap}$ from Step 5's sizing rule, and $P_{decap,leakage}$ from the fact that decoupling capacitors, like any other MOS structure, carry their own small static leakage even while performing their intended job.

Every Step's Cost Term Feeds Back Into One Comparison Step 1's simplified equation gains the terms Steps 2 through 5 each introduced P_CMOS,real = C_CMOS·V_dd²·f_CMOS + P_decap,leakage A_CMOS,real = A_active + A_guardring (Step 3) + A_decap (Step 5) Step 1's idealized P_CMOS≈C_C·V_dd²·f never included these this step reinserts them before judging the crossover's actual margin P_HMOS = I_DD·V_dd + C_HMOS·V_dd²·f_HMOS (unchanged since Step 1) HMOS's own equation needed no revision — it never promised a free lunch the comparison's fairness depends entirely on CMOS's side being complete does the margin survive once every cost is counted? Section 2 runs the numbers at representative 1980s values

## 2. Run the Numbers at Representative 1980s Values and Show the Margin Survives

Using values representative of early-1980s process generations — $V_{dd}=5\text{ V}$, a few hundred thousand gates per die, clock frequencies in the low single-digit megahertz range for the complex logic this crossover era targeted — the aggregate static term $I_{DD}V_{dd}$ in a comparably dense HMOS design reaches the scale of several watts for a gate count that would need it switching continuously, while CMOS's dynamic term at the same gate count and frequency, even after adding $A_{guardring}$'s modest area overhead and $P_{decap,leakage}$'s small additional static contribution, remains a fraction of that total. The guard-ring and decoupling-capacitance costs this series quantified in Steps 3 and 5 are real, and they are not negligible for a layout engineer budgeting die area — but measured in the same units Step 1 used to declare the crossover, neither cost is large enough to erase the margin by which CMOS's total power beats HMOS's at this density.

$$\frac{P_{total,HMOS}}{P_{total,CMOS,real}}\gg 1 \quad\text{at 1980s density, even with every added cost included}$$

This is the honest version of the claim Step 1 made more simply: the crossover is real, it survives the full accounting this series has since performed, and the costs Steps 2 through 5 identified are genuine engineering burdens a CMOS designer must budget for — they are not large enough to be a counterargument to the crossover itself.

The Added Costs Are Real but Small Next to the Margin Real Diagram — HMOS's static term against CMOS's dynamic term plus every Step 2-5 addition HMOS TOTAL dominated by I_DD·V_dd CMOS DYNAMIC C_C·V_dd²·f only CMOS + ALL COSTS +decap leak +guard-ring area ADDED COSTS ARE A SMALL SLIVER, NOT A COUNTERWEIGHT P_HMOS/P_CMOS,real ≫ 1 holds even after every Step 2-5 term is included the crossover survives its own full accounting

## 3. State What This Verification Closes, and What It Leaves for Step 7

This step closes the accounting loop this series opened in Step 1 and carried through Steps 2 to 5: it is not enough to declare a crossover and move on, nor is it enough to enumerate costs without checking whether they threaten the conclusion that motivated finding them. This project's established tradeoff-accounting pattern — 1974 DRAM's Step 9, 1978 HMOS's Step 7 — always closed its own loop this way, and this series now does the same: the margin by which CMOS wins at 1980s density is wide enough to absorb every cost Steps 2 through 5 identified, so the crossover this series set out to document is confirmed, not merely asserted.

What this step does not do is compare CMOS against the specific successor process this series' own Step 1 already gestured toward — HMOS-II, the second-generation push the 1978 series' own Step 8 described as approaching NMOS's physical limit. That comparison, against a more aggressively scaled NMOS generation rather than first-generation HMOS, is a harder test of the same margin, and the next step takes it up directly: does CMOS's advantage still hold against the most optimized NMOS variant this project's lineage ever produced, or does HMOS-II's own scaling narrow the gap enough to matter.

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