Common Centroid Layout

Common-centroid layout is the answer to a problem no amount of careful transistor sizing can solve on its own: two devices meant to be identical are never placed at exactly the same point on a wafer, and every gradient the fabrication process leaves behind — in oxide thickness, dopant concentration, temperature, mechanical stress — varies smoothly across the die, so two nominally matched transistors sitting at different locations inherit different values of whatever that gradient happens to be at each one's position.

The geometry works because a linear gradient, integrated symmetrically around a shared center, cancels exactly rather than approximately. Split each of the two devices A and B into two half-sized halves, and arrange the four pieces in a cross pattern — A1, B1, B2, A2 — so that the point exactly between A1 and A2, and the point exactly between B1 and B2, are the same physical location on the die. Any process parameter that varies linearly across that neighborhood contributes equally and oppositely to the two halves of each device, so the average seen by A equals the average seen by B to first order, regardless of which direction the gradient happens to run. This is why the arrangement is named for sharing a centroid: both devices are centered on the same point, so both average the same local neighborhood of the gradient.

What common-centroid layout does not fix is exactly as important as what it does, and conflating the two is a common design error. The technique cancels systematic, smoothly varying gradients — oxide thickness, temperature, stress — because those are, to first order, linear across the small distances involved. It does nothing for random mismatch: the local, statistically independent variation from dopant placement and line-edge roughness that differs even between two devices placed at the exact same location, which is what the Pelgrom model describes and quantifies as inversely proportional to the square root of device area. Common-centroid layout and larger device area are two separate remedies for two separate mismatch mechanisms, and a design that only applies one while assuming it covers both will find the uncovered error showing up in silicon.

Precision analog layout stacks several of these disciplines together because each one addresses a mechanism the others cannot touch. Dummy devices placed around the edges of a matched array absorb the different etch loading and neighbor environment that boundary devices otherwise see compared to interior ones — an edge effect entirely separate from any smooth die-wide gradient. Orientation matching keeps both halves of a matched pair aligned to the same crystallographic and lithographic axis, since stress and some litho proximity effects are directional rather than purely radial or linear. None of these substitute for common-centroid geometry, and common-centroid geometry does not substitute for any of them — a differential pair, a current mirror, or a resistor ladder meant to hold tight matching in silicon routinely uses common-centroid placement, adequate device area, dummy guard structures, and orientation matching simultaneously, because each layer of mismatch demands its own specific countermeasure.

This closes the same chain of reasoning the rest of this series has been building toward from a different direction. Where autozeroing and charge-injection cancellation deal with time-domain errors a circuit creates against itself, and kT/C noise is a thermodynamic floor no layout trick can remove, common-centroid layout addresses a spatial error: two devices meant to be equal, physically separated on a die that is never perfectly uniform. It is the layout-level discipline sitting alongside the circuit-level and physics-level disciplines the rest of this cluster covers — all four problems exist simultaneously in any real precision analog design, and all four need their own specific answer.

Common-centroid layout is proof that a mismatch problem can sometimes be solved with pure geometry rather than with more silicon or more power — arranging two devices so they share a center turns a gradient from an error source into something that cancels itself out by construction. It is also proof that no single trick covers every mismatch mechanism at once; the technique earns its place in the layout toolkit precisely because it solves one problem completely, and leaves the others for their own dedicated fix.