Common Gate Amplifier
# Common-Gate Amplifier: Source Input, Drain Output
A common-gate amplifier applies its input at a MOS transistor’s source, takes its output at the drain, and holds the gate near AC ground. It offers a relatively low input resistance and noninverting voltage gain. These properties make it useful for current-signal interfaces and RF input stages.
“Common” refers to the gate’s small-signal role. The gate normally needs a DC bias to establish the operating point; AC grounding means that its signal voltage remains nearly fixed over the intended band.
## 1. Follow the signal polarity
*Conceptual NMOS stage. A separate bias feed establishes the gate DC voltage; the capacitor keeps it quiet for AC. The input connection represents a signal superimposed on source bias. The current sink has high small-signal impedance; body connection and practical coupling details are omitted.*
When the source input rises while the gate stays fixed, VGS falls. Drain current decreases, the drop across RD decreases, and the drain voltage rises. Input and output therefore move in the same direction in the low-frequency voltage-gain sense.
Neglecting body effect, output conductance and parasitic capacitance, the source-port signal current is approximately i in = gm v in. The input resistance is Rin ≈ 1/gm, and the unloaded voltage gain from the source node to the drain is Av ≈ +gm RD. With an additional resistive output load, use the parallel combination of RD and that load in this simplified gain expression.
## 2. Use gm to estimate the input loading
*The curve is calculated from Rin = 1/gm. It is an analytical starting point, not measured or PDK-simulated RF data. A 50-ohm match is only a candidate under these assumptions.*
For gm = 20 mS, the ideal input resistance is 50 ohms. With RD = 500 ohms, gain from the source node is about +10 V/V. If the signal generator has a 50-ohm series resistance, the matched input divides its open-circuit voltage by two. Gain measured from that open-circuit generator voltage is then about +5 V/V. State the reference point when quoting gain.
The input-resistance estimate is sensitive to circuit conditions. With finite transistor output resistance ro and a resistive drain load RD, but still neglecting body effect, Rin = (ro + RD)/(1 + gm ro) for an ideal high-impedance source-bias sink and an unloaded gate. It approaches 1/gm when gm ro is large and RD is small relative to ro. A very large drain load can change the result substantially.
If the body is held at AC ground, body transconductance contributes to source-port conductance. Source-bias circuitry, gate-bias impedance, coupling components and parasitic capacitances also affect the impedance seen by the actual signal source.
## 3. Compare the three basic MOS stages
| Stage | Signal input → output | Low-frequency voltage polarity | Typical input behavior |
|---|---|---|---|
| Common source | Gate → drain | Inverting | High resistive input impedance |
| Common gate | Source → drain | Noninverting | Low resistance, often estimated by 1/gm |
| Common drain / source follower | Gate → source | Noninverting | High resistive input impedance |
These are qualitative starting points. Device capacitances, feedback and loading determine the actual impedance and bandwidth.
## 4. Understand its role in RF and cascode circuits
A common-gate RF stage can provide a useful input termination through transconductance. Increasing gm usually changes current consumption, transistor size and capacitance, so matching is part of a larger design tradeoff. Input matching alone does not guarantee an acceptable noise figure, linearity or stability; measure or simulate those quantities separately across the required band.
In a cascode, a common-source transistor drives the source of an upper common-gate transistor. The upper device limits signal motion at the lower device’s drain, reducing feedback through its gate-drain capacitance and increasing output resistance. Stacking devices also consumes voltage headroom. The complete cascode must keep both transistors in their intended operating regions.
## 5. Verify the actual stage
Check DC gate and source bias, drain current and saturation margin across process, supply and temperature. Use a small-signal source-port test to extract input impedance with the real drain load and bias network connected. At RF, include package and layout parasitics and inspect S-parameters, noise, stability and large-signal behavior.
A good verification report distinguishes source-node gain from generator-to-output gain, identifies the output load, and states the frequency range over which the low-frequency model remains useful. Source degeneration is a different use of the source terminal: it adds feedback impedance to a gate-driven stage.
## References
- [Analog Devices: Activity — The Common Gate Amplifier](https://wiki.analog.com/university/courses/alm1k/alm-lab-cg) — circuit operation and approximate gain and impedance.
- [JKU Institute for Integrated Circuits: Low Noise Amplifiers](https://iic-jku.github.io/radio-frequency-integrated-circuits/slides/lna.html) — RF input matching and LNA tradeoffs.
- [JKU: Analog Integrated Circuit Design](https://iic-jku.github.io/analog-circuit-design/aicd.html) — cascode stage analysis and transistor models.