Constant-Field Scaling
Constant-field scaling is the specific set of rules for shrinking a MOSFET that keeps the electric fields inside the device approximately unchanged as its dimensions get smaller, by reducing physical sizes, supply voltage, and doping in a coordinated way. Formulated by Robert Dennard and colleagues at IBM in the early 1970s, it is the theoretical backbone that made transistor scaling a disciplined, predictable process rather than ad hoc shrinking. The guiding principle in the name is the key: if the internal fields stay constant while the device shrinks, the transistor continues to behave well and its improvements in speed and power follow in a clean, calculable way.
The core prescription is to scale all the relevant quantities by the same factor so that electric fields remain constant, which prevents shrinking from distorting the device's physics. If a dimension is reduced by some factor, then other dimensions, the gate-insulator thickness, the supply voltage, and the doping concentrations are adjusted by corresponding factors chosen so the electric fields within the transistor stay about the same as before. Keeping the fields constant matters because the transistor's behavior depends heavily on those fields; letting them rise as the device shrinks would push the device toward breakdown and misbehavior, while holding them constant keeps the smaller transistor a faithful, well-behaved smaller version of the larger one.
The power of constant-field scaling is that it made the benefits of shrinking predictable, converting miniaturization into an engineering roadmap. Because the rules specify exactly how voltage, dimensions, and doping move together, the resulting changes in switching speed, power per transistor, and density follow in known proportions each time the device is scaled. This predictability is what allowed the industry to plan generations ahead, because designers could anticipate roughly what each new smaller node would deliver. The disciplined relationship between size reduction and performance gain is precisely what turned scaling from a hopeful trend into a dependable plan.
Constant-field scaling is closely tied to, but conceptually distinct from, the broader notion of Dennard scaling and the general practice of MOSFET scaling. The general practice of scaling is simply making transistors smaller; constant-field scaling is one particular, principled recipe for how to do it so the fields stay fixed and the benefits follow cleanly. It is the formal rule set that underlay the industry's power-and-performance gains for many generations, and it is why a specific set of proportional adjustments, rather than arbitrary shrinking, became the standard way to advance a technology node.
The eventual breakdown of constant-field scaling is one of the most important inflection points in modern chip history. The scheme requires reducing supply voltage in step with dimensions, but voltage could not keep falling indefinitely without transistors failing to switch properly and without leakage currents becoming significant. When voltage scaling stalled while dimensions kept shrinking, the clean constant-field relationship broke, power density began rising, and the industry could no longer rely on the simple recipe. The end of straightforward constant-field scaling is a major reason chip design shifted toward multiple cores, new transistor structures, and power-focused techniques, making this rule set important both for the era it enabled and for the consequences of its limits.
Read constant-field scaling as the recipe that kept shrinking honest: Dennard's prescription to reduce dimensions, voltage, and doping together so the transistor's internal fields stay fixed, which made each smaller generation a predictably faster, lower-power version of the last — until voltage could no longer follow and the clean relationship broke.