copper cmp
**Copper CMP (Chemical Mechanical Planarization)** is the **post-electroplating polishing process that removes excess copper overburden from the wafer surface while simultaneously planarizing the metal interconnect layer to within 2–10 nm of global flatness** — the enabling step that makes multi-level copper damascene interconnect possible. Without copper CMP, copper overburden would prevent subsequent lithography and interconnect layers from printing correctly, and the dishing and erosion side-effects of copper CMP are among the most actively managed yield and reliability concerns at every advanced node.
**Copper CMP in Damascene Flow**
```
1. Dielectric deposition (low-k, SiCOH)
2. Trench + via etch (pattern wires and vias)
3. Barrier/seed deposition (TaN/Cu or Ru/Cu)
4. Copper electroplating (overfill trenches by 500–2000 nm)
5. *** COPPER CMP *** ← this process
a. Bulk Cu removal (fast, high pressure)
b. Barrier CMP (slow, selective to dielectric)
c. Buffing (smooth, reduce scratches)
6. Post-CMP clean
7. Inspection + next layer deposition
```
**Three-Step Copper CMP**
| Step | Slurry Type | Rate | Purpose |
|------|-----------|------|--------|
| Bulk Cu | Oxidizer + abrasive (high Cu rate) | 500–1000 nm/min | Remove overburden quickly |
| Barrier | Selective slurry (Cu:barrier:oxide ≈ 1:5:1) | 50–200 nm/min | Remove TaN/Ta without over-eroding oxide |
| Buffing/touch-up | Dilute or barrier slurry | Slow | Smooth surface, reduce micro-scratches |
**Slurry Chemistry**
- **Oxidizer**: H₂O₂ (most common) — oxidizes Cu surface to Cu²⁺ oxide layer.
- **Complexing agent**: Glycine, BTA (benzotriazole) — controls passivation and dissolution.
- **Abrasive**: Silica (SiO₂) or alumina (Al₂O₃) nanoparticles, 30–200 nm — mechanically abrades the softened oxide layer.
- **pH**: Typically acidic (pH 2–4) for Cu dissolution; near-neutral for barrier step.
**Defects in Copper CMP**
| Defect | Cause | Impact | Mitigation |
|--------|-------|--------|------------|
| Dishing | Cu polishes faster than dielectric → Cu recesses below surface | Increased resistance, reliability risk | Reduce CMP pressure; endpoint control |
| Erosion | Dense Cu arrays lose dielectric → topology drops | Planarity loss, next layer litho issues | DFM dummy fill to equalize pattern density |
| Corrosion | Slurry attacks Cu grain boundaries | Voids, increased resistance | BTA inhibitor, post-CMP clean |
| Scratches | Agglomerated abrasives | Electrical shorts, yield loss | Slurry filtration, pad conditioning |
| Residues | Cu or barrier particles remain | Short circuits between lines | Post-CMP clean (brush scrub + chemistry) |
**Endpoint Detection**
- **Motor current**: As Cu clears and barrier is exposed, friction changes → motor current change → stop signal.
- **Optical**: In-situ reflectance measures Cu clearing — thin Cu films change reflectance as Cu thins to zero.
- **Eddy current**: Non-contact Cu film thickness measurement → monitor thinning in real time.
**Dishing and Erosion Control**
- Dishing increases with wider Cu lines → wide copper fills are most at risk.
- Erosion increases with dense small-pitch Cu arrays → power grid regions most at risk.
- **DFM solution**: Insert dummy Cu fill in sparse areas + dummy dielectric slots in dense areas → equalize density → reduce CMP non-uniformity.
- **Process solution**: Barrier step endpoint optimization → stop before excess dielectric removal.
**Advanced Nodes: Challenges**
- At 5nm and below, Cu line widths are 10–20 nm → absolute dishing budget is <1 nm.
- Alternative metals (Ru, Mo, Co) reduce CMP complexity at narrow lines (less dishing tendency).
- Low-k dielectric (k < 2.5) is mechanically fragile → CMP pressure must be reduced → slower removal rate → throughput impact.
Copper CMP is **the precision planarization heartbeat of every copper interconnect process** — its ability to simultaneously achieve near-atomic-scale flatness, high throughput, and defect-free surfaces across the full 300mm wafer determines the interconnect quality, resistance, and reliability of every advanced semiconductor chip manufactured today.