coverage driven verification

**Coverage-Driven Verification (CDV)** is the **systematic approach to measuring and closing verification completeness using quantitative coverage metrics** — ensuring that all critical design scenarios, corner cases, and functional states have been exercised before tapeout, replacing the ad-hoc "run more tests and hope" methodology with data-driven verification management. **Types of Coverage** **Code Coverage** (automatic, tool-measured): - **Line Coverage**: Was every line of RTL code executed? - **Branch Coverage**: Were both branches of every if/else taken? - **Toggle Coverage**: Did every signal transition both 0→1 and 1→0? - **FSM Coverage**: Were all states visited? Were all state transitions taken? - **Expression Coverage**: Were all conditions in complex expressions evaluated independently? **Functional Coverage** (user-defined, intent-specific): - **Coverpoints**: Define which values of specific signals must be observed. - **Cross Coverage**: Define which combinations of values must be observed together. - **Transition Coverage**: Define which value sequences must occur. - **Example**: For a FIFO design, functional coverage might require: - FIFO full condition observed. - FIFO empty condition observed. - Simultaneous read and write at full. - All data widths (8, 16, 32 bit) exercised. **CDV Workflow** 1. **Coverage Plan**: Document lists all scenarios to verify (derived from spec). 2. **Covergroup Implementation**: Translate plan into SystemVerilog covergroups. 3. **Constrained Random Simulation**: UVM testbench generates random-but-legal stimulus. 4. **Coverage Collection**: Simulator records which coverpoints were hit. 5. **Coverage Analysis**: Identify coverage holes — scenarios not yet exercised. 6. **Directed Tests**: Write targeted tests to hit remaining coverage holes. 7. **Coverage Closure**: All coverpoints hit → verification goal met. **Coverage Goals for Tapeout** | Metric | Typical Threshold | |--------|------------------| | Line coverage | > 98% | | Branch coverage | > 95% | | Toggle coverage | > 90% | | FSM coverage | 100% states, > 95% transitions | | Functional coverage | 100% (all defined coverpoints hit) | - Waivers required for any unreachable coverage holes (documented justification). Coverage-driven verification is **the industry-standard methodology for verification closure** — it transforms verification from an art into a measurable engineering discipline where quantitative coverage metrics determine when a design is ready for silicon.