critical path monitor

**A critical path monitor (CPM)** is an **on-die circuit that replicates the actual timing-critical paths** of the chip and continuously measures their delay — providing real-time feedback on how much timing margin exists under current operating conditions (voltage, temperature, process, aging). **Why CPMs Are Better Than Ring Oscillators** - **Ring oscillators** use a chain of identical inverters — they indicate general transistor speed but don't capture the complexity of real logic paths. - **Real critical paths** involve different gate types (NAND, NOR, MUX, XOR), different stack heights, different wire loads, and different loading patterns. - A CPM **replicates the actual critical path topology** — providing a much more accurate indication of whether the chip can meet its timing target. **How a CPM Works** 1. **Path Replica**: A copy of the critical path's gate chain is implemented on-die, with matched gate types, sizes, and approximate loading. 2. **Launch Signal**: A clock edge launches a transition through the replica path. 3. **Capture**: At the other end, the signal arrival is compared against a reference clock (the same or a delayed version of the launch clock). 4. **Margin Measurement**: The time difference between signal arrival and the reference clock indicates the **timing margin** (slack): - Positive margin: the path is faster than required — voltage can be reduced. - Zero or negative margin: the path is at or past its limit — voltage should be increased or frequency reduced. **CPM Architecture** - **Delay Chain**: Replica of the critical logic path — may include configurable delay stages to adjust the target delay. - **Phase Detector**: Compares the delayed signal against the reference clock — determines early/late/on-time. - **Digital Logic**: Processes the phase detector output and reports margin to the AVS controller. - **Calibration**: The CPM can be calibrated against actual STA results to ensure its delay accurately tracks the real critical path. **CPM Applications** - **AVS (Adaptive Voltage Scaling)**: The CPM provides the most accurate speed feedback for voltage adjustment: - If CPM reports positive margin → reduce voltage → save power. - If CPM reports low/negative margin → increase voltage → maintain performance. - This is more accurate than using ring oscillators because CPMs directly measure timing margin. - **Aging Detection**: As transistors degrade (NBTI, HCI), the CPM path slows down — the decreasing margin directly indicates aging. - **Droop Detection**: During voltage droop events, CPM margin drops — can trigger protective actions (clock stretching). - **Silicon Validation**: CPMs verify that actual silicon timing matches design predictions — identifying pessimism or optimism in the STA flow. **CPM Challenges** - **Path Selection**: Which critical paths to replicate? The critical path changes with PVT — multiple CPMs tracking different path types may be needed. - **Accuracy**: The CPM is a replica, not the actual path — differences in loading, coupling, and routing create some tracking error. - **Area**: CPMs are larger than ring oscillators — each one replicates a significant logic chain. Critical path monitors are the **gold standard** for on-die timing measurement — they provide the most direct and accurate indication of a chip's actual timing margin under real operating conditions.