custom layout design

**Custom / Full-Custom Layout** — manual, transistor-by-transistor layout design where engineers hand-optimize every feature for maximum performance, density, or analog precision. **When Custom Layout Is Used** - **SRAM bitcells**: Must be absolute minimum area. Every nanometer matters - **High-speed I/O**: SerDes analog front-end, clock buffers — timing-critical - **Analog blocks**: Op-amps, ADCs, DACs, bandgap references — require precise matching - **Standard cells**: The cells themselves are custom-designed (then instantiated millions of times) - **Critical datapaths**: CPU ALU, multiplier — when automated PnR isn't good enough **Custom Layout Process** 1. Circuit simulation and sizing (SPICE) 2. Manual polygon-level layout in Cadence Virtuoso 3. DRC check → fix violations iteratively 4. LVS check → ensure layout matches schematic 5. Parasitic extraction → re-simulate with parasitics 6. Iterate until performance targets met **Skills Required** - Deep understanding of process technology and design rules - Knowledge of parasitic effects and their impact on performance - Spatial reasoning and pattern optimization - Years of experience to become proficient **Productivity** - Custom layout: ~10–50 transistors per engineer-day - Automated PnR: Millions of cells per hour - Only used where the performance/area benefit justifies the enormous time investment **Custom layout** is the most labor-intensive part of chip design — but for the few critical structures that demand it, nothing else achieves the same results.