DAC Clock Jitter

# DAC Clock Jitter: Timing Error Becomes Analog Error

DAC clock jitter is variation in the timing of conversion events relative to an ideal clock reference. Even if the digital code values are correct, moving their analog update instants can change the output waveform. Depending on its spectrum and the converter architecture, timing error can appear as phase noise, broadband error or discrete sidebands.

The relevant timing is at the conversion process. A clean oscillator specification alone does not establish the jitter seen after clock buffers, routing, internal PLLs and converter circuitry.

## 1. Compare actual edges with their reference

DAC clock update edges with time interval errorsFive ideal clock rising edges are compared with illustrative displaced rising edges. Reference lines indicate the ideal positions. A delta t bracket illustrates timing error at one edge. Pulse widths and timing displacements are exaggerated; not measured data.The right value can arrive at the wrong timeIdeal update instants versus displaced edges · not to scaleIDEALACTUALΔt: edge timing errorTiming uncertainty can become phase error or spurs.Random and periodic timing errors have different spectra.A constant delay is latency; a varying delay creates jitter.

*Conceptual edge displacements, exaggerated for visibility. This illustration does not specify period-jitter statistics, pulse-width behavior or a measured clock spectrum.*

Time-interval error compares actual edge times with a chosen ideal timing grid. Period jitter describes variation in individual periods; cycle-to-cycle jitter compares neighboring periods. These are different measurements, so their RMS values should not be substituted blindly into the same calculation.

A constant delay shifts every edge equally and is latency. A constant frequency offset creates an accumulating timing difference relative to a fixed reference. Define how frequency offset and drift are removed before reporting jitter. The analysis bandwidth and reference-clock relationship also matter.

## 2. Use a small-phase model with explicit assumptions

Calculated sinusoidal jitter error limit versus frequencySmall phase sinusoid model SNR equals minus twenty log ten of two pi output frequency times RMS timing error. Logarithmic frequency axis one to one thousand megahertz. One picosecond and one hundred femtosecond curves differ by twenty decibels. At one hundred megahertz and one picosecond approximate SNR is sixty four decibels. Not a universal DAC specification.Higher output frequency is more timing-sensitiveCalculated small-phase sinusoid model · jitter-only SNR4060801001201101001000SNR / dBf out / MHz100 fs RMS1 ps RMSSNR ≈ −20 log10(2π f out σt)At 100 MHz and 1 ps: about 64 dB in this model.Actual DAC sensitivity depends on pulse mode and noise transfer.

*Calculated example for a sinusoid undergoing a small timing perturbation, with zero-mean RMS timing error σt. The timing error is assumed suitably independent of the signal. The chart is a model, not a prediction for every DAC architecture or measurement band.*

For x(t) = A sin(2πfOUTt), a small time displacement gives an error approximately x′(t)Δt. Under the usual independent-error assumptions, the RMS error-to-signal ratio is approximately 2πfOUTσt. The corresponding jitter-only ratio is SNR ≈ −20 log10(2πfOUTσt).

At 100 MHz and 1 ps RMS, the model gives approximately 64.0 dB. Reducing timing uncertainty to 100 fs gives approximately 84.0 dB. Increasing output frequency by a decade lowers this model’s ratio by 20 dB for fixed σt. These are calculations for sinusoidal time perturbation, not a universal DAC SNR ceiling.

A DAC’s sampled pulse shape, reconstruction, noise transfer and chosen image can change its sensitivity. Delta-sigma feedback DACs and return-to-zero outputs may have timing-error mechanisms that are not captured by treating the final sinusoid as merely time-shifted. Use the selected converter’s architecture and characterization when setting a clock requirement.

## 3. Inspect the noise spectrum as well as RMS jitter

Random timing variation can spread energy around a generated tone. A periodic timing modulation produces discrete sidebands rather than a featureless noise floor. Two clocks with the same integrated RMS number can therefore create different close-in noise or spur behavior.

Phase-noise integration requires stated offset-frequency limits. For small phase noise, the RMS time error associated with a clock carrier fCLK is σt = σφ/(2πfCLK), where σφ is integrated RMS phase in radians. Converting single-sideband phase noise into phase variance requires the appropriate two-sideband factor and consistent units.

The frequency in that phase-to-time conversion is the clock carrier; the frequency in the simple sinusoidal error model is the analog signal frequency. Confusing those two frequencies gives the wrong estimate. Internal PLLs and clock-noise transfer functions also affect how external phase noise reaches the analog output.

## 4. Build the clock path as part of the analog system

Clock-input slew, signal amplitude, termination, reflections, supply noise and coupled interference can all influence edge timing. Follow the device’s clock-input requirements. Inspect the signal at the receiving pins rather than assuming that the source waveform arrives unchanged.

Uncorrelated timing-error contributions can sometimes be combined by root-sum-square under a suitable model. Correlated sources require covariance terms; their RMS values cannot automatically be added in quadrature. Avoid counting the same noise twice when specifications already include downstream circuitry.

Digital interpolation raises the DAC core rate but does not automatically eliminate clock sensitivity. The actual output frequency, selected pulse mode, internal clocking and reconstruction path determine the result. Improving digital code resolution also does not remove timing error.

## 5. Measure the DAC output under representative conditions

Use output tones across the required band, including the highest intended analog frequency. Record core rate, interpolation mode, internal PLL settings, output pulse mode and clock-source configuration. Measure close-in phase noise, integrated noise and relevant spurs with stated bandwidths rather than compressing every result into one SNR number.

Compare with a suitable reference clock or a controlled change in clock quality. Keep output level, termination and supply conditions fixed so their effects can be distinguished. Check instrument residual noise and reference correlation; a shared reference can make some timing error cancel in a measurement.

A complete assessment separates clock-induced error from quantization noise, DAC thermal noise, distortion, DAC glitch impulse and output-network effects. Improve the contributor that actually limits the required measurement, then verify the full path again.

## References

  • [Analog Devices: Analyzing and Managing Supply Noise and Clock Jitter in High-Speed DAC Phase Noise](https://www.analog.com/en/resources/analog-dialogue/articles/analyzing-and-managing-the-impact-of-supply-noise-and-clock-jitter-on-high-speed-dac-phase-noise.html) — clock-to-output phase-noise behavior and other contributors.
  • [Analog Devices: Analyzing Audio DAC Jitter Sensitivity](https://www.analog.com/en/resources/technical-articles/analyzing-audio-dac-jitter-sensitivity.html) — architecture-dependent jitter sensitivity and spectral effects.
  • [Texas Instruments: Clocking High-Speed Data Converters](https://www.ti.com/document-viewer/lit/html/SSZTBT2/GUID-BA0725E4-29B8-40CE-97FE-FCFE479122E1) — clock-system considerations and converter timing.

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