DAC Differential Output

# DAC Differential Output: Read the Pair and Each Pin

A differential DAC output carries the intended signal in the difference between two analog output nodes. In a common current-steering arrangement, a fixed total current is divided between complementary outputs. A suitable load converts those currents into voltages for the next circuit.

The difference voltage and the voltage of either pin relative to ground are separate quantities. Understanding both prevents errors in signal amplitude, termination and compliance checks.

## 1. Follow the complementary currents

Complementary DAC currents into equal grounded resistorsIdeal sourcing DAC steers fixed total current I FS between outputs A and B. Each output drives equal resistor R to ground. Current fractions alpha and one minus alpha produce differential voltage R I FS times two alpha minus one, with constant common mode R I FS over two. Other topologies need different bias and sign conventions.One total current, two complementary pathsSimplified sourcing DAC · equal resistors to groundCURRENT DACI A + I B = I FSI A = α I FSI B = (1−α) I FSV ARV BRMeasure V A − V B between the two pins.V diff = R(I A − I B) = R I FS (2α − 1)V cm = (V A + V B)/2 = R I FS / 2Valid for this ideal matched-load sourcing model.

*Ideal single-ended load on each of two complementary sourcing outputs. This is an explanatory model, not a universal DAC connection recommendation. It omits output resistance, bias circuitry and transient behavior.*

Let IFS be the total steered current and α the fraction sent to output A. Then IA = αIFS and IB = (1 − α)IFS. For equal resistors R returned to ground, VA = RIA and VB = RIB. The differential signal is VDIFF = VA − VB = RIFS(2α − 1).

The common-mode voltage is VCM = (VA + VB)/2 = RIFS/2. It is constant in this ideal model because the total current and both loads are constant. Real output impedance, mismatch and switching effects can produce deviations.

Current-sinking outputs, loads returned to a supply or bias node, and active current-to-voltage converters require their own polarity and bias equations. Verify the actual device’s recommended interface before using the grounded sourcing model.

## 2. Calculate both kinds of voltage

Calculated differential and common mode DAC voltagesFor total ten milliamps and fifty-ohm grounded loads, alpha one quarter gives A zero point one two five volts B zero point three seven five and differential minus zero point two five. At alpha one half each pin zero point two five and differential zero. At alpha three quarters values exchange and differential plus zero point two five. Common mode remains zero point two five volts.Differential swing is not pin-to-ground swingCalculated example · I FS = 10 mA · R = 50 Ω per pinαV AV BV diffV cm0.250.125 V0.375 V−0.250 V0.250 V0.500.250 V0.250 V0 V0.250 V0.750.375 V0.125 V+0.250 V0.250 VBoth pin voltages stay positive while their difference changes sign.For any V cm and V diff:V A = V cm + V diff/2 · V B = V cm − V diff/2Check compliance at each pin, not only across the pair.

*Calculated normalized steering fractions, not a claim that these fractions correspond exactly to specific codes in every finite-resolution DAC. No named device limits are assumed.*

With IFS = 10 mA and R = 50 ohms per pin, α = 0.25 gives VA = 0.125 V and VB = 0.375 V. Their difference is −0.250 V, while their average is +0.250 V. Exchanging the current fractions reverses the difference without making either grounded pin voltage negative.

For any pair, VA = VCM + VDIFF/2 and VB = VCM − VDIFF/2. These identities are useful even when the simple current model no longer applies. A bipolar differential signal does not necessarily mean either individual pin swings below ground.

When two pins have equal and opposite AC excursions around a constant common mode, the differential AC amplitude is twice that of either individual pin. State whether amplitude means peak, peak-to-peak or RMS, and whether it is measured single-ended or differentially. Signal power also depends on the actual load; a voltage-amplitude comparison alone does not define delivered power.

## 3. Check loading and compliance separately

A pair of grounded resistors is not interchangeable with a resistor connected only between the outputs. A floating differential load may leave the common-mode bias undefined unless another path establishes it. At high frequency, a transformer or bias network can provide the required paths, but its DC behavior and reflected impedance must be analyzed.

A receiver, probe, cable termination or filter adds loading. Two nominal 50-ohm terminations in parallel look different from one 50-ohm resistor. Include all paths when calculating current-to-voltage gain and pin voltage.

DAC output compliance constrains the allowed voltage at each current pin under the specified conditions. A differential swing that appears modest can still drive one pin outside its window if the common-mode level is unsuitable. Check both pins over signal excursions, startup and relevant update transients.

## 4. Understand rejection and its limits

An ideal differential receiver subtracts identical disturbances on the two inputs. Balanced DAC signaling can therefore reduce common-mode error at the receiver. Actual rejection depends on receiver common-mode rejection, matching, routing, loading and frequency.

Unequal gain or delay converts some common-mode content into differential error. The receiver must also tolerate the input common-mode range; subtraction does not excuse an overloaded input. Noise generated independently in the two paths is not automatically canceled.

Some distortion components may cancel in a suitably balanced differential implementation. That benefit depends on symmetry and the mechanism producing the error; it is not a blanket guarantee that every even-order harmonic or switching glitch disappears.

## 5. Choose the conversion interface deliberately

A differential amplifier can convert the pair to another differential level or to a single-ended output, subject to gain, headroom, noise and bandwidth limits. A transformer or balun can provide AC coupling and impedance conversion where its frequency range is suitable, but cannot pass DC.

A transimpedance stage can hold a DAC current node near a controlled potential while generating voltage elsewhere. Its feedback network, input capacitance and amplifier dynamics affect stability and settling. Use an interface recommended for the DAC architecture and verify the complete signal path.

If only one output is observed, still terminate or bias the unused output as required by the data sheet. Leaving it floating or shorting it without checking the architecture can alter compliance, dynamic behavior or device operation.

## 6. Verify the pair in the real circuit

Measure VA and VB with probes that provide suitable loading and timing alignment. Form VDIFF and VCM consistently, and distinguish a differential probe’s bandwidth from its common-mode rejection at frequency. Instrument mismatch can create an apparent imbalance that is not in the DAC.

Check gain, offset, common-mode variation, distortion and DAC settling time with representative codes and signals. Record full-scale current setting, bias, termination, output mode and measurement bandwidth. Compare both pin voltages and the differential waveform with the same model; a good differential trace alone can hide an individual-pin problem.

## References

  • [Analog Devices AD9760 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD9760.pdf) — complementary current outputs, resistive conversion and differential operation; limits apply to the stated device conditions.
  • [Analog Devices AN-912: Driving a Center-Tapped Transformer with a Balanced Current-Output DAC](https://www.analog.com/en/resources/app-notes/an-912.html) — transformer interface and load interpretation.
  • [Analog Devices: Why is an unterminated DDS output not a useful voltage signal?](https://www.analog.com/en/resources/faqs/faq_why_cannot_i_see_a_signal_aoutput_of_my_dds.html) — current-to-voltage conversion and output loading.

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