DAC Intersymbol Interference

# DAC Intersymbol Interference: When Earlier Updates Still Matter

DAC intersymbol interference (ISI) describes unwanted interaction between successive output intervals: the waveform associated with one update depends on earlier activity. A converter and its output network have memory, so correct code values alone do not establish the instantaneous analog result.

The term covers related but distinct situations. Linear bandwidth limits can spread pulse responses into neighboring intervals. In high-speed DAC design, transition-dependent switching behavior can also produce nonlinear memory errors. Distinguish those mechanisms before choosing a model or remedy.

## 1. Start with a controlled history comparison

Same DAC target approached from two previous levelsCalculated single-pole response to target zero point five. From initial zero, output reaches zero point four at one update interval T. From initial one, output reaches zero point six. Residual fraction after T is zero point two. Normalized units, not measured device data.Same target. Different starting history.Calculated first-order response toward normalized target 0.500.51Update at 0TStarting at 1 → 0.6 at TStarting at 0 → 0.4 at TTarget = 0.520% of the starting error remains after one interval.An identical target does not imply an identical early output.This linear memory example is not a nonlinear DAC model.

*Calculated first-order linear example. The target is normalized to 0.5. Two runs begin at different settled levels, 0 and 1. The model leaves 20% of the initial error after an interval T; it is not measured DAC behavior.*

For y(t) = x + (y0 − x)exp(−t/τ), holding target x = 0.5 gives different early outputs for different initial states. If exp(−T/τ) = 0.2, the endpoints are 0.4 from below and 0.6 from above. The residual error is opposite in sign even though the requested current code is identical.

This observation demonstrates memory, not by itself nonlinearity. A linear time-invariant system responds by superposition of pulse responses. If those pulses overlap the chosen observation instants, earlier symbols contribute to the current result. In a communications system, the complete transmit/channel/receive pulse response determines whether that overlap causes ISI at the decision times.

## 2. Follow the memory across intervals

Calculated decay of two previous DAC output historiesEndpoint recurrence y n equals zero point four plus zero point two times previous y. Initial zero gives zero point four, zero point four eight, zero point four nine six. Initial one gives zero point six, zero point five two, zero point five zero four. Both converge to target zero point five. Purely linear illustrative model.History fades while the target is heldy[n] = 0.8 × 0.5 + 0.2 × y[n−1] · endpoint samplesInitialAfter TAfter 2TAfter 3T00.4000.4800.49610.6000.5200.504Both approach 0.500; the difference shrinks by 0.2 each interval.One coefficient describes both histories here.If response depends nonlinearly on code or transition history,a single linear settling model may no longer explain the error.

*Calculated endpoints of the same first-order model with the target held constant. Here y[n] means the end of interval n; it is not the instantaneous DAC code value.*

The recurrence is y[n] = (1 − α)x[n] + αy[n−1], where α = exp(−T/τ). For α = 0.2 and constant x = 0.5, the endpoints from zero are 0.400, 0.480 and 0.496. Starting from one gives 0.600, 0.520 and 0.504. The difference between the two histories falls by a factor of 0.2 each interval.

A real DAC path may have several poles, ringing, slew limitations or slower recovery effects. The recurrence is an intentionally simple demonstration of linear settling memory. It cannot predict arbitrary switching distortion or establish a device’s effective resolution.

## 3. Identify transition-dependent DAC errors

In a current-steering DAC, different current cells may switch at slightly different times. Rise and fall behavior can differ, and internal node voltages can depend on prior switching. If the resulting error depends on code, transition direction or history in a way that violates linear superposition, a single fixed impulse response is insufficient.

Such dynamic errors can create harmonics, intermodulation and pattern-dependent spurs even when static code measurements look acceptable. A static INL correction table does not automatically correct a history-dependent transfer. Likewise, a single-step settling measurement does not characterize every possible code sequence.

Not every timing error is ISI. A common shift of all update instants relates to DAC clock jitter or latency, while mismatched timing among unit elements can cause a different distortion mechanism. DAC glitch impulse describes an update transient; whether it creates history-dependent error requires examining the sequence and recovery behavior.

## 4. Separate the converter from the surrounding path

The output buffer, reconstruction filter, termination and interconnect can all contribute memory. A filter deliberately spreads a pulse in time to meet a spectral target. That spreading is not automatically a converter defect. An end-to-end design can accommodate it through suitable pulse shaping, observation timing or equalization.

Check output compliance, loading and supply behavior when comparing histories. An overloaded amplifier or a pin driven outside its intended voltage window can create recovery effects that a nominal linear model misses. Keep clock rate, output mode and measurement conditions fixed so differences can be attributed to the intended test variable.

## 5. Test a family of histories

Choose a common target and reach it from several previous codes. Then test sequences that share the same immediate transition but differ in earlier samples. This separates sensitivity to the last step from longer memory. Record traces at a consistent time reference and compare both the transient waveform and the error at the actual observation instant.

Use representative multitone, modulated or pseudorandom sequences as appropriate. Inspect dynamic metrics such as intermodulation, spectral regrowth or error-vector magnitude with stated bandwidths. A repeated pattern can create coherent spurs, so one pattern is not a complete characterization.

For model validation, compare predicted and measured responses across held-out histories. A fixed linear model should explain its intended operating range with one consistent set of parameters. Systematic code-dependent residuals motivate a more detailed physical or nonlinear model; they are not a reason to relabel every mismatch as noise.

## 6. Match the remedy to the mechanism

More settling time, suitable bandwidth and stable loading can reduce residual linear memory at an observation instant. Equalization can compensate a known linear response within practical headroom and noise limits. Unit-cell timing alignment, switch design and internal-node control address other dynamic mechanisms.

Calibration or predistortion must represent the memory it is meant to correct. Validate any improvement across frequency, amplitude, histories and operating conditions. Dynamic element matching redistributes element mismatch; it does not automatically remove switching-history errors. Evaluate its actual selection sequence and analog transitions together.

## References

  • [Beauchamp and Chugg: Improved Analysis of Current-Steering DACs Using Equivalent Timing Errors](https://arxiv.org/abs/2203.08939) — timing mismatch and nonlinear distortion in current-steering DACs.
  • [Analog Devices: Current-Steering Digital-to-Analog Converters](https://wiki.analog.com/university/courses/tutorials/cmos-dac-chapter) — converter architecture and practical dynamic effects.
  • [Analog Devices AN74: Component and Measurement Advances Ensure 16-Bit DAC Settling Time](https://www.analog.com/media/en/technical-documentation/application-notes/an74f.pdf) — precision settling and measurement considerations.

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