Double Diffused Silicon Mesa 1956 Surface Clean Polish

# Surface Clean and Polish the Wafer: Removing Everything a Diffusion Furnace Would Otherwise Copy Into the Crystal

## 1. Why a Furnace Cannot Be Trusted to Ignore a Dirty Surface

Every diffusion step that follows this one introduces dopant atoms through the wafer's exposed surface, which means any contamination, mechanical damage, or native oxide irregularity sitting on that surface at this moment becomes a permanent feature of the finished junction, not a correctable one. A diffusion furnace does not distinguish between the silicon lattice and whatever foreign atoms or surface defects happen to be present when the dopant source arrives; a scratch from wafer handling becomes a locally enhanced diffusion path, a trace metal contaminant becomes a deep-level trap inside the finished base or emitter, and a non-uniform native oxide becomes a non-uniform dopant introduction rate across the wafer. The surface condition entering the furnace is carried forward into the electrical behavior of every transistor the wafer eventually becomes:

$$J_{\text{leak}} \propto N_t \,\sigma\, v_{\text{th}}\, n_i$$

where $N_t$ is the density of contamination-induced trap states, $\sigma$ their capture cross-section, and $n_i$ the intrinsic carrier concentration — a relation that says plainly that trap density introduced at this step shows up later as leakage current in a device that, on paper, should have been clean.

A Surface Flaw Here Becomes a Permanent Electrical Feature Later the furnace copies whatever condition it finds, it does not clean up after itself UNCLEANED SURFACE, ENTERING FURNACE scratches, trace metals, uneven native oxide furnace diffusion step non-uniform junction, trapped defects, local leakage CLEANED SURFACE, ENTERING FURNACE bare, uniform, contaminant-free silicon furnace diffusion step uniform junction depth, predictable electrical behavior this step changes nothing about dopant profile; it only guarantees the later steps can be trusted to behave as modeled

## 2. Real Diagram: The Clean/Polish Sequence Itself

The cleaning and polishing done at this step is a sequence, not a single action: mechanical lapping removes saw damage from wafer slicing, a chemical-mechanical polish produces an optically flat, damage-free surface, and a final chemical clean (an oxidizing acid clean of the kind that strips organic residue and trace metals) leaves a thin, uniform native oxide the wafer can carry into the next step without it acting as an uncontrolled mask.

Three Sub-Stages, One Step each removes a different category of defect the furnace would otherwise inherit LAPPING removes saw-damage layer from slicing coarse abrasive, flattens bulk surface leaves microscopic subsurface strain CHEMICAL-MECHANICAL POLISH removes the strained layer lapping left behind fine abrasive slurry, optically flat finish exposes undamaged single-crystal surface CHEMICAL CLEAN strips organics and trace metal contaminants oxidizing acid clean, leaves thin uniform oxide ready for a controlled, repeatable diffusion sequence, not substitutes: skipping any one leaves a defect category the next stage cannot remove

## 3. Why This Step Matters More Here Than It Did for the Germanium Process

The 1954 diffused-base germanium process this project has already documented also required a clean starting surface, but the consequence of skipping that discipline is sharper here, because this process asks the surface to support two separate diffusions whose combined depth and grading precision directly determine the drift field strength that makes this device faster than a uniformly doped base. A contamination-induced trap or a residual scratch does not just raise leakage the way it would in a simpler structure — it locally distorts the dopant gradient the next several steps are trying to engineer on purpose, degrading the very drift field this entire device exists to create. Silicon's higher intrinsic resistance to surface-state formation compared with germanium makes this step more forgiving than it would be on the earlier material, but it does not make it optional: the drift-graded base downstream depends on a surface this clean to begin with.

Step 2 does not add anything to the wafer; it removes everything that would otherwise be added to it by accident, so that every dopant atom introduced from this point forward arrives exactly where the process intends and nowhere else.

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