Double Diffused Silicon Mesa 1956 Mask Active Device Area

# Mask the Active Device Area: Deciding What the Next Step Is Allowed to Destroy

## 1. Why a Mask Has to Exist Before an Etch Can Be Trusted

This step applies a protective dot — wax or photoresist — over each location on the wafer where a finished transistor's emitter-base-collector junction stack is meant to survive, leaving everything else exposed for the mesa etch that follows. The two diffusions completed in the previous six steps cover the entire wafer surface uniformly; nothing about them, by itself, defines where one transistor ends and the next begins, or where the finished device's lateral boundary will be. Mesa isolation depends entirely on a chemical etch removing silicon between devices, and a chemical etch cannot distinguish "silicon I should remove" from "silicon I should not" unless something physically covers the areas meant to remain. The mask pattern therefore directly defines device pitch and area:

$$A_{\text{mesa}} = \pi r_{\text{mask}}^2$$

for a circular mask dot of radius $r_{\text{mask}}$, with the un-masked area between dots equal to the wafer surface minus the sum of every mesa's protected area — and every dimension of the finished device's footprint traces back to a decision made at this step, not at the etch step that comes next.

A Uniform Wafer Becomes a Pattern of Protected Dots before this step, the whole surface is identical; after it, two categories exist: masked and exposed TOP VIEW, WAFER SURFACE AFTER MASKING masked dot: this becomes one mesa exposed field: etched away next step r₝ᴸᴸᴯ Aᴲᴲᴸᴰ = πr² — device pitch and area are fixed here, not at the etch step the etch that follows can only ever remove what this pattern leaves exposed

## 2. Real Diagram: Applying the Mask Over the Finished Diffusion Stack

By this point in the 1956 process, each location on the wafer already contains the complete vertical junction stack from Steps 1 through 7 — collector, graded base, shallow emitter — stacked uniformly across the surface. Masking does not touch that vertical structure at all; it only decides, in the lateral dimension, which columns of that stack survive the next step and which do not.

Cross-Section: Mask Sits Above an Already-Finished Junction Stack the vertical structure from Steps 1–7 is untouched by this step collector, N-type bulk, from Step 1 graded base, from Steps 3–5 shallow emitter, from Steps 6–7 mask mask mask exposed: removed next step exposed: removed next step three identical vertical stacks, one lateral pattern — this step produces the pattern only

## 3. Why This Step Has No Equivalent Step in the 1954 Diffused-Base Process's Original Documentation

The 1954 diffused-base germanium process this project has already documented used a similar masking idea for its own device isolation, but the stakes of a misaligned or oversized mask differ here because of how much electrical structure this step's pattern has to preserve intact. An oversized mask here does not just waste wafer area; left wide enough, it can leave adjacent mesas electrically connected through an unetched channel, shorting two transistors' collectors together through the shared N-type bulk they were both diffused into — a failure mode the next step's etch is specifically responsible for preventing, but one this step's mask geometry sets the risk for in the first place. The mask pattern is therefore not a cosmetic preparation step; it is the lateral blueprint the rest of this device's physical isolation depends on.

Step 8 does not remove anything or change any junction; it draws, in wax or photoresist, the only boundary the next step is permitted to respect.

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