Ddr5 PHY Training Sequence

Before a DDR5 or LPDDR5X channel can move a single data bit, the memory controller and the DRAM run a fixed calibration sequence that finds the exact voltage and timing window where each signal reads reliably, because at 6400+ MT/s and beyond the margin for being wrong shrinks to picoseconds. Every boot runs this sequence from scratch rather than trusting a prior calibration, since temperature drift, voltage sag, and even which DIMM slots are populated shift the optimal sampling point enough to flip bits if the controller just reused yesterday's settings. JEDEC specifies the full sequence for DDR5; LPDDR5 and LPDDR5X mobile variants run an equivalent flow adapted for point-to-point topologies inside phones and laptops rather than slotted DIMMs.

Write leveling exists because DDR5's fly-by topology means the clock signal reaches each DRAM chip on a module at a slightly different time, so without correction the write strobe and the data it is supposed to align with drift out of phase as you move down the command bus. The controller sweeps DQS phase per DRAM until each chip reports the strobe landing centered on its own clock edge, then locks that offset in; read gate training runs an analogous sweep in the other direction, since the controller — not the DRAM — has to find the valid sampling window for data coming back on reads. DQ/DQS deskew tightens this further bit by bit within a single byte lane, because process variation means not even every DQ pin inside one chip arrives at exactly the same time.

An eye diagram is what you get when you overlay thousands of consecutive bit transitions on top of each other, and the open area in the middle — the "eye" — is literally the usable margin left for the receiver to sample correctly. Its vertical opening is voltage margin: how far apart a 1 and a 0 sit before noise can flip one into the other. Its horizontal opening is timing margin: how much the sampling clock can drift before it samples too close to a transition edge. Both openings shrink as data rate climbs, because the same channel noise and reflections now eat into a bit period that has gotten physically shorter — at DDR5-6400 a single bit lasts about 156 picoseconds, and LPDDR5X pushes past 8533 MT/s with proportionally less room to spare, which is exactly why Micron, SK hynix, and Samsung DRAM datasheets increasingly quote eye-mask compliance rather than a single timing number: the whole shape of the eye, not one edge of it, is what a PHY training sequence is actually trying to maximize.

The whole calibration sequence has to re-run, in whole or in part, far more often than once per boot — DDR5 supports periodic re-training to track thermal drift during operation, and a system that skips it will see its eye slowly close until read or write errors start appearing under load. AMD and Intel platform memory controllers both expose training-sequence logs and eye-diagram margin readouts through vendor tools specifically so board designers can catch a channel that trained with thin margins in the lab before it ships; a channel that passes training once but shows a tight eye is a latent field failure waiting for whichever DIMM runs hottest. The real measure of a DDR5 or LPDDR5 channel's health is not whether it links up at boot — training usually succeeds even on a marginal channel — but how much eye margin is left over once it does.