debug trace infrastructure design

**Debug and Trace Infrastructure Design** is **the on-chip instrumentation system that provides visibility into processor execution, bus transactions, and hardware state during software development and post-silicon validation — enabling engineers to observe, control, and diagnose complex SoC behavior without disrupting real-time operation**. **Debug Access Architecture:** - **JTAG (IEEE 1149.1)**: standard 4/5-wire debug interface (TCK, TMS, TDI, TDO, optional TRST) — provides serial scan access to debug registers, boundary scan cells, and on-chip debug modules at 10-50 MHz - **SWD (Serial Wire Debug)**: ARM-specific 2-wire alternative to JTAG (SWDIO, SWCLK) — reduces pin count while maintaining full debug capability through packet-based protocol - **Debug Access Port (DAP)**: protocol translation layer connecting external JTAG/SWD to internal debug bus — ARM CoreSight DAP includes JTAG-DP and SW-DP interfaces with multi-drop support for debugging multiple cores through a single port - **cJTAG (IEEE 1149.7)**: compact JTAG using 2-wire interface with advanced features — supports star topology, concurrent debug of multiple TAPs, and higher bandwidth than standard JTAG **CoreSight Debug Architecture:** - **Debug Components**: each CPU core contains breakpoint/watchpoint units (4-8 hardware breakpoints, 2-4 watchpoints), debug control registers, and halt/step/resume logic accessible through the debug APB bus - **Cross-Trigger Interface (CTI)**: enables synchronized debug operations across multiple cores and subsystems — trigger events (breakpoint hit, watchpoint match) propagated to other cores for correlated debugging - **Trace Sources**: ETM (Embedded Trace Macrocell) generates compressed instruction trace (address + branch history) and data trace (load/store addresses and values) — ITM (Instrumentation Trace Macrocell) provides printf-style software trace output - **Trace Links**: ATB (AMBA Trace Bus) connects trace sources through funnels, replicators, and FIFOs to trace sinks — configurable topology allows routing trace from any source to any sink **Trace Capture Methods:** - **ETB (Embedded Trace Buffer)**: on-chip SRAM buffer (4-64 KB) stores most recent trace data in circular buffer — limited capacity means only last few thousand instructions captured, but zero-latency capture with no external hardware - **TPIU (Trace Port Interface Unit)**: parallel or serial trace port streams trace data off-chip through dedicated pins (1-32 bit parallel or SWO single-wire output) — requires external trace probe hardware but provides unlimited capture depth - **System Trace**: STM (System Trace Macrocell) captures hardware events, bus transactions, and software instrumentation at timestamps — enables system-level performance analysis and correlation with CPU trace **Debug and trace infrastructure is the essential development tooling layer that transforms opaque silicon into observable, debuggable systems — typically consuming 2-5% of die area, this investment pays back enormously by reducing time-to-first-working-software from months to weeks.**