decoupling capacitor

**On-Chip Decoupling Capacitor Placement** is the **integration of capacitive elements (MOSCAP, well-cap) into chip die — distributed near switching logic to reduce transient voltage droop — optimizing density, leakage, and placement for maximum effectiveness — a key component of on-chip power delivery**. Decap placement directly impacts PDN performance. **MOSCAP (Gate Oxide Capacitor) vs Well-Cap** On-chip capacitors include: (1) MOSCAP (metal-oxide-semiconductor capacitor) — thin gate oxide acts as dielectric, large polysilicon or metal top plate, large area diffusion bottom plate, capacitance value high (~1-10 fF/µm²), but thin oxide (<2 nm at advanced nodes) makes leakage high (~100 nA/µm² at nominal Vdd), (2) well-cap (junction capacitor) — p-well to substrate (or n-well to substrate) depletion capacitance, lower capacitance density (~0.1-0.5 fF/µm²) but much lower leakage. MOSCAP provides denser decoupling but leakage penalty; well-cap is lower-capacitance but lower-leakage. Design uses mix: MOSCAP in non-critical areas (acceptable leakage), well-cap in power-constrained blocks. **Decap Density Requirement** On-chip decap density is expressed as capacitance per unit area: target ~1-5 fF/µm² (equivalent to 1-5 pF per 100 µm × 100 µm region). Density requirement depends on: (1) current transient magnitude (larger transient needs larger cap), (2) frequency of transient (higher frequency needs lower impedance, more cap), (3) target impedance (lower target requires more cap). Typical allocations: (1) high-speed CPU core ~5 fF/µm², (2) general logic ~2-3 fF/µm², (3) peripheral ~1 fF/µm². Total on-chip decap at 28 nm node is ~1-5% of die area; at 7 nm node, ~5-10% (higher density needed for tighter timing). **Leakage vs Capacitance Trade-off** MOSCAP leakage increases exponentially with temperature and voltage: I_leak ∝ exp(-qVg / kT). At 125°C and nominal Vdd, MOSCAP leakage can be 10-100x higher than at 25°C. High total MOSCAP leakage (~100 mA-1 A for large decap density) directly impacts power consumption. Design trade-off: (1) maximize MOSCAP (tight decap density) for best impedance, but high leakage, (2) minimize MOSCAP (lower density) for low leakage, but PDN impedance loose (voltage droop risk). Optimization aims for balanced point: use MOSCAP only where needed (high-switching areas), use well-cap elsewhere. At advanced nodes with stricter power budgets, MOSCAP usage is carefully managed. **Thin-Oxide MOSCAPs** Modern MOSCAPs use minimum-thickness gate oxide (~0.5-1.5 nm at 7 nm node) for maximum capacitance. Thin oxide has exponentially higher leakage current: I_leak ∝ exp(-t_ox). Risk: if MOSCAP oxide is defective (pinhole, defect), gate-to-channel shorts, turning MOSCAP into resistor (wasting power). Defect density in thin oxide increases, making yield risk non-negligible (~0.01-0.1% defect rate). Mitigation: (1) smaller MOSCAP cells (if one fails, local impact only), (2) higher specification and testing (100% MOSCAP test at manufacturing), (3) redundancy (multiple decaps in region, one can fail without fatal impact). **Well Decap (Filler Cell Decap)** Well-cap is often integrated into filler cells (empty space in standard cell rows) for area efficiency. Filler cells contain: (1) logic function (for routing), or (2) well-cap only (passive decoupling). Well-cap filler is placed wherever logic allows (not in critical paths). Placement density is limited by routing constraints (space needed for signal metal). Well-cap decap is lower-density than dedicated MOSCAP but provides additional margin with minimal area cost. **Antenna Rule for Decap Cells** Decap cells (especially MOSCAP, with large gate and diffusion area) are subject to antenna rules: if decap area (gate perimeter) is large without proportional diffusion tie-off, charge accumulation during gate etch can damage gate oxide. Antenna mitigation for decaps: (1) place via/metal jumpers (diode-connected diffusion) to provide discharge path during etch, (2) limit decap size (smaller decaps have lower antenna ratio), (3) place decap cells late (after antenna-critical gate etch, if possible). Antenna-induced yield loss from decaps is a known challenge; careful cell design and placement mitigates risk. **Placement Strategy (Near Switching Logic, Power Pins)** Decap placement is optimized: (1) place near high-switching logic (minimize path impedance from decap to load), (2) place near power pins (decaps connected to power rails via short vias), (3) cluster decaps in dense switching regions (identify hot spots from simulation, add extra decaps). Placement algorithm: (1) estimate local switching current density (via simulation), (2) identify regions with high current demand, (3) insert decaps in those regions (respecting physical constraints like routing). Iterative: if droop simulation shows violation at specific location, add decaps nearby. **Decap Effectiveness at High Frequency** At high frequency, decap effectiveness is limited by parasitic inductance (ESL — effective series inductance). Decap impedance Z = ESL × ω + (1 / (ω × C)). At very high frequency (>GHz), ESL dominates and Z ≈ ESL × ω (impedance increases with frequency). To reduce ESL, decaps must be: (1) placed close to load (short via, lower L), (2) multiple vias per decap (parallel vias reduce L by ~√N for N vias), (3) direct connection to power plane (low-inductance path). ESL reduction is critical: 50% ESL reduction halves impedance at GHz frequencies. **Decap Supply Noise Reduction Analysis** Decap effectiveness is simulated via: (1) transient current injection simulation — inject current transient (step, ramp), measure voltage response, (2) with decaps — voltage ripple reduced (decaps source current, reducing dV/dt), (3) without decaps — voltage ripple larger. Simulation quantifies: voltage reduction per unit decap, optimal placement. At circuit level, decap current is: I_decap = C × dV/dt + ESL^(-1) × V. Larger decap and lower ESL reduce voltage transients. **Summary** On-chip decoupling capacitor placement is a detailed optimization, balancing capacitance density, leakage, area, and placement strategy. Continued advances in thin-oxide MOSCAPs and filler-integrated decaps drive improved on-chip PDN performance.