Deep Submicron

Deep-submicron describes semiconductor technology with critical dimensions well below one micrometer, where shrinking a drawing is no longer a sufficient explanation of transistor behavior. In this glossary, the term introduces the transition toward the 0.35, 0.25, and 0.18 micrometer generations and the engineering changes that made them practical. It is a descriptive category rather than one process specification: a node name does not identify every gate length, contact size, and wire pitch. The preceding 0.8 and 0.5 micrometer generations provide useful context. Chenming Hu’s published teaching material places 0.5, 0.35, 0.25, and 0.18 micrometer technology generations in 1992, 1995, 1997, and 1999, respectively; these are an educational timeline, not universal introduction dates for every manufacturer. [Source: Chenming Hu, Chapter 7 teaching slides](https://www.chu.berkeley.edu/wp-content/uploads/2020/01/Chenming-Hu-ch7-slides.ppt-Compatibility-Mode-Repaired.pdf).

The scaling idea predates the commercial process generations that later made it familiar. Robert Dennard and colleagues’ 1974 paper, “Design of Ion-Implanted MOSFET’s With Very Small Physical Dimensions,” developed scaling relationships and examined how doping profiles and shallow source/drain regions supported smaller devices. The authors reported experimental polysilicon-gate transistors with channel lengths down to 0.5 micrometers. That research result must be distinguished from a later high-volume manufacturing node: demonstrating a transistor does not establish the yield, interconnect stack, circuit library, or production readiness of an entire process. The paper also used two-dimensional modeling to investigate short-channel behavior, showing that electrostatic design was already integral to the scaling problem. [Source: Dennard et al., 1974](https://research.ibm.com/publications/design-of-ion-implanted-mosfets-with-very-small-physical-dimensions).

Shorter channels make control of the off state as important as drive current in the on state. The drain can influence the source-side barrier, producing drain-induced barrier lowering, while current still flows below the nominal threshold voltage. Making the gate dielectric thinner strengthens gate control but eventually increases tunneling leakage. These mechanisms are distinct: subthreshold current travels through the channel, whereas gate tunneling crosses the dielectric. They explain why a process description needs more than a minimum dimension. Threshold voltage, dielectric thickness, junction profiles, operating voltage, and the intended leakage budget all matter. [Source: Chenming Hu, Chapter 7, scaling and leakage](https://www.chu.berkeley.edu/wp-content/uploads/2020/01/Chenming-Hu_ch7.pdf).

Deep-ultraviolet lithography is an enabling tool, but its wavelength is not a synonym for the technology node. Krypton-fluoride excimer lasers provide 248 nm light; argon-fluoride systems use 193 nm. The printed pattern also depends on the optical system and the imaging process. A particularly useful historical check is ASML’s 2000 announcement of a KrF scanner optimized for 130 nm design rules: 248 nm illumination did not restrict the nominal design rules to 248 nm. Accordingly, entries on KrF lithography, 248 nm lithography, resolution enhancement, and process-node dimensions should explain their relationships without treating these quantities as interchangeable. [Sources: ASML, light and lasers](https://www.asml.com/en/technology/lithography-principles/light-and-lasers), [ASML’s 2000 KrF scanner announcement](https://www.asml.com/en/news/press-releases/2000/asml-introduces-krf-lithography-scanner-optimized-for).

Copper wiring illustrates how scaling demanded a manufacturable materials system as well as smaller transistors. IBM’s 1997 IEDM paper, “Full copper wiring in a sub-0.25 μm CMOS ULSI technology,” documented an integrated CMOS/copper technology. IBM’s later retrospective distinguishes the 1997 announcement and functional CPU prototypes from the manufacturing ramp in mid-1998. That distinction prevents a research milestone, announcement, and commercial production date from collapsing into one event. It also gives the copper-interconnect branch of this glossary a concrete historical anchor: the meaningful achievement was integrating copper wiring into working chips, not simply observing that copper conducts electricity. [Sources: IBM’s 1997 paper](https://research.ibm.com/publications/full-copper-wiring-in-a-sub-025-mm-cmos-ulsi-technology), [IBM’s 2017 manufacturing retrospective](https://research.ibm.com/publications/20-years-of-cu-beol-in-manufacturing-and-its-future-prospects).

The era’s transitions did not arrive as one compulsory package. AMD’s 1998 annual report, filed in 1999, described a 180 nm technology with six aluminum interconnect layers while discussing copper as a further development. This provides a useful counterexample to the idea that every deep-submicron process automatically used copper. Intel’s June 1999 announcement separately activated its 300 mm wafer development program and described future production plans. Wafer diameter, wiring material, lithography wavelength, and transistor dimensions therefore need separate histories. For the topics that follow, the useful organizing question is what changed, in whose process, and at which stage of development or production. [Sources: AMD’s annual report](https://ir.amd.com/financial-information/sec-filings/content/0001012870-99-000892/EX-13.txt), [Intel’s June 1999 wafer-program announcement](https://www.intel.com/pressroom/archive/releases/1999/Cn060999.htm).

Read deep-submicron as the transition in which smaller CMOS dimensions required coordinated advances in transistor control, pattern transfer, materials integration, and circuit design.