Deep Submicron CMOS Scaling 1990s Confront the New Scaling Wall Below One Micron

# Deep Submicron CMOS Scaling (1990s): Step 1 — Confront the New Scaling Wall Below One Micron

## 1. The Geometric Shrink Alone Stops Being Enough

Through the 1980s, the `cmos_logic_1980s` series traced CMOS's rise on the strength of a fairly simple recipe: shrink every lateral and vertical dimension by a constant scaling factor, drop supply voltage to match, and density, speed, and power all improve together in the Dennard pattern. That recipe depended on a quiet assumption — that the physics inside the device cell scaled as cleanly as the layout did. As gate lengths crossed below roughly one micron and continued toward 0.5 micron and then 0.25 micron through the 1990s, that assumption broke down in several places at once: the electric fields inside a short channel no longer fell in proportion to the shrink, the gate oxide could not be thinned at the same relative rate as the channel without risking direct tunneling, and the wiring layered on top of the transistors — which had scaled benignly for a decade — started adding its own delay that rivaled the transistor's own switching time.

## 2. Why "Just Shrink It Again" Stopped Working

Simple geometric (constant-field) scaling calls for supply voltage to fall by the same factor as every linear dimension, keeping internal electric fields constant generation to generation. In practice, 1990s processes kept supply voltage higher than that rule recommended for several generations — first at 5V, Section-by-section detailed in later steps of this series, because board-level compatibility with existing 5V logic families and I/O standards made an abrupt voltage drop commercially disruptive even when physics wanted one. The result was that internal fields rose rather than held constant as channel lengths shrank, and every failure mode whose rate depends on field — hot-carrier injection, oxide wearout, drain-junction breakdown — got measurably worse at exactly the moment density pressure demanded shorter channels. This series is about the decade of targeted process fixes CMOS needed to keep shrinking despite that field-vs-voltage mismatch, not a new transistor family: the planar CMOS inverter from the 1980s series survives into the 1990s, but almost everything around its channel, drain, gate stack, and wiring changes.

## 3. What This Series Covers, and What It Leaves for Later

Steps 2 through 7 of this series work through the two most pressing device-level problems deep submicron geometries created — hot-carrier degradation and gate-oxide scaling limits — and the lightly-doped-drain and channel-engineering fixes 1990s processes adopted for them. Steps 8 through 14 shift to the back end of the chip: silicide and salicide contacts to tame rising sheet resistance, and multilevel interconnect scaling, CMP planarization, and the copper-transition pressure that RC delay created once wires, not transistors, became the pacing element in many critical paths. Steps 15 through 18 cover shallow trench isolation (replacing the LOCOS isolation the `mosfet_scaling_1970s` series introduced), halo/pocket implants for threshold control, and the voltage-scaling path from 5V toward 3.3V and below. Steps 19 and 20 close the series by assembling these pieces into a representative 0.25-micron-class node and situating deep submicron CMOS as the foundation under the 1990s PC and workstation microprocessor boom — leaving the 2000s' further scaling crises (which begin where this series' voltage and leakage trends are still heading) for a future series.