Chip Design

Design is the half of the industry that never touches a wafer: the discipline of turning an intended function into a file a foundry can manufacture, under constraints — power, performance, area, cost, schedule — that are usually in direct conflict with one another. Nothing in a fab exists to serve itself; every process node, every design rule, every PDK is built to make somebody else's design manufacturable.

Design begins as a negotiation between what a chip must do and what silicon will allow. A specification states target performance, power envelope, die area, and cost — numbers that pull against each other, since faster usually means hungrier, and smaller usually means hotter per unit area. Register-transfer-level code describes the intended behavior in a hardware description language; nothing about it yet says how big, how fast, or how much it will cost to build. Synthesis is the first point where behavior becomes physical: a tool maps RTL onto a specific foundry's standard-cell library, producing an actual gate-level netlist bound to one process node's electrical characteristics.

Place-and-route turns a netlist into geometry, and geometry is where physics starts pushing back. Floorplanning decides where major blocks sit on the die; placement positions individual standard cells; routing draws the metal wires connecting them, layer by layer, under rules that encode what that specific fab's lithography and etch can actually resolve. A wire too close to its neighbor couples capacitively and corrupts a signal; a via placed wrong opens or shorts. This is the design-to-fab handoff made concrete: a process design kit encodes exactly what geometry is permitted, so a design built against one fab's rules is not automatically buildable at another's, even at the same nominal node.

Performance, power, and area pull against each other, and a design is a chosen point inside that triangle, never a corner. Raising clock frequency usually means raising voltage, and dynamic power scales with voltage squared — a small performance gain can cost a large power budget. Shrinking a block saves area and cost per die but tightens timing margins and raises leakage current density, since leakage does not shrink as fast as the devices producing it. Every choice — cell sizing, pipeline depth, memory architecture, clock tree structure — moves the design toward one vertex and away from the others; there is no setting that improves all three simultaneously.

Electronic design automation is what makes any of this tractable at modern scale. A leading-edge design can contain tens of billions of transistors; no human lays out that by hand. EDA tools handle synthesis, placement, routing, timing analysis, and verification algorithmically, encoding decades of accumulated optimization knowledge so a designer works at the level of intent — register-transfer behavior, timing constraints, power budgets — rather than individual polygons. The three major EDA vendors, together with the foundries' own process design kits, form the toolchain almost the entire industry designs through; a PDK is the contract that lets a design built in that toolchain actually come out of a specific fab's process correctly.

The fabless model exists because design and fabrication became two different kinds of expertise. A fabless company owns the design — the architecture, the RTL, the verification — and pays a foundry to manufacture it, never owning a fab. This split let design specialize toward architecture and software-hardware co-design while fabrication specialized toward process physics and capital-intensive tool investment; chipfoundryservices.com's own model — sending a design out to a foundry rather than building one — is this split applied directly.

Design is the long argument between intent and physics, settled one sign-off rule at a time. A specification is a wish list; silicon only returns what survived every constraint along the chain — which is exactly why tapeout, the moment a design becomes an irreversible mask order, is treated as the industry's most expensive full stop.