design rule check drc

**Physical Verification (DRC/LVS)** is the **sign-off verification process that ensures the chip layout conforms to all foundry manufacturing rules (DRC) and that the layout electrically matches the intended schematic (LVS) — the final gate between design completion and tapeout, where a single DRC violation can cause a systematic yield failure affecting every die, and a single LVS error means the chip does not function as designed**. **Design Rule Check (DRC)** DRC verifies that every geometric feature in the layout complies with the foundry's manufacturing design rules — hundreds to thousands of rules specifying: - **Minimum Width**: Every metal, poly, diffusion, and via feature must exceed the minimum width for its layer. Sub-minimum features may not resolve in lithography. - **Minimum Spacing**: Adjacent features on the same layer must maintain minimum clearance to avoid shorts from process variation. - **Enclosure/Extension**: Vias must be enclosed by a minimum margin of metal above and below. Contacts must extend beyond the active region. - **Density**: Metal density on each layer must fall within a specified range (20-80%) for CMP planarity. The tool inserts dummy fill to meet minimum density. - **Multi-Patterning**: At 7nm and below, adjacent features must be assigned to different patterning masks (coloring) — violated features cannot be manufactured with the available lithography. - **Antenna Rules**: Long metal traces connected to transistor gates accumulate charge during plasma etch, potentially damaging the thin gate oxide. Antenna rules limit the ratio of metal area to gate area, requiring antenna diode insertion for protection. **Layout Versus Schematic (LVS)** LVS extracts the circuit topology from the physical layout (recognizing transistors from overlapping poly/diffusion, extracting connectivity from metal/via layers) and compares it to the source schematic or netlist. Discrepancies include: - **Device mismatches**: Different W/L, wrong Vt flavor, missing devices. - **Net mismatches**: Opens (discontinuous metal), shorts (bridging between nets), missing vias. - **Port mismatches**: Missing or extra pins at the block boundary. LVS must report zero errors for tapeout — a clean LVS is the definitive proof that the physical layout implements the intended design. **Tools and Flow** Siemens Calibre and Synopsys IC Validator are the two industry-standard physical verification tools. Both are foundry-certified for sign-off — meaning the foundry has validated that the tool's rule deck produces correct results for their process. Sign-off DRC/LVS runtime for a full chip can be 12-48 hours on compute clusters with thousands of CPU cores. **DRC Waiver Process** Some DRC violations may be intentionally accepted (waived) after engineering review — for example, density violations in analog blocks or spacing violations at IP boundary interfaces. Waivers require formal documentation and foundry approval, as each waived violation carries a yield or reliability risk. Physical Verification is **the non-negotiable manufacturing compliance check** — the final mathematical proof that the layout is both manufacturable (DRC clean) and functionally correct (LVS clean) before committing millions of dollars to mask fabrication.