die attach

**Die attach** is the process of bonding a silicon die to its package carrier — a leadframe, organic substrate, or ceramic — forming the thermal, mechanical, and electrical joint that governs reliability and heat dissipation for the life of the device. Die-attach material choice directly sets the junction-to-case thermal resistance and determines whether the assembly survives the thermal cycling demanded by automotive, industrial, and data-center qualification standards. ```svg ``` **The thermal resistance budget starts at die attach.** The total thermal path from silicon junction to ambient is the sum of multiple resistances: die-attach layer (theta_da), thermal interface material between die and heat spreader (theta_TIM1), integrated heat spreader to cooler (theta_TIM2), and the cooler itself. For a 600W TDP GPU or AI accelerator, the total junction-to-ambient resistance must be below 0.25-0.5 C/W. Die-attach thermal conductivity ranges from 1-4 W/m·K for filled epoxy to 200-300 W/m·K for sintered copper — a 100x spread that directly controls how much headroom remains for the rest of the thermal stack. **Epoxy die attach** is the lowest-cost option and dominates consumer and low-power applications. A filled silver-epoxy paste is dispensed onto the die paddle, the die is placed face-up by a pick-and-place machine with 5-10 micrometer accuracy, and the assembly is cured at 150-175°C for 60-90 minutes. The main failure mode is delamination under thermal cycling due to the large CTE mismatch between silicon (2.5 ppm/C) and copper leadframe (17 ppm/C). Void fraction must be kept below 5% of the attach area; voids concentrate heat and create local hot spots that accelerate electromigration and dielectric breakdown. **Soft solder (SAC305)** offers 55 W/m·K thermal conductivity and is reflow-processable at 250-260°C. It is standard for flip-chip packages and mid-range discrete semiconductors. AuSn 80/20 eutectic solder (57 W/m·K, 280°C liquidus) is used in RF, laser diode, and hermetic ceramic packages where flux contamination is unacceptable and the joint must be both electrically and thermally conductive. **Sintered silver and sintered copper** are transforming power semiconductor packaging. Silver sintering yields 150-250 W/m·K thermal conductivity — 5x better than SAC solder — and withstands junction temperatures above 300°C without creep-driven fatigue. This is critical for silicon carbide (SiC) MOSFETs in 800V EV inverters, where the junction temperature swings by 100°C or more per power cycle and traditional solder fails after 1000-2000 cycles. Sintered silver survives more than 10,000 thermal cycles and can enable double-sided cooling by bonding both the top copper clip and the bottom drain pad simultaneously. The process requires applying pressure (5-40 MPa) during sintering at 200-300°C and demands silver metallization on the die backside — typically Ti/Ag or Ni/Ag sputtered stack. **Scanning acoustic microscopy (SAM)** is the post-attach inspection standard. Focused ultrasound detects delamination and voids as reflections at the die-attach interface, achieving 100-micrometer lateral resolution. Industry specifications typically require less than 5% total void area and no single void exceeding 25% of the attach area, per JEDEC JESD22-A104 or IPC-7711/7721 criteria. **The transition from wire-bond to flip-chip to hybrid bonding** changes the die-attach picture at each step. Wire-bond dies sit face-up on the carrier with full backside contact to the die-attach material. Flip-chip dies are face-down with C4 bumps as the primary mechanical and electrical connection, and underfill encapsulant provides the bulk of the mechanical joint to the substrate. SoIC and hybrid-bonded 3D stacks eliminate the die-attach material entirely, bonding copper pads directly to copper pads at sub-micrometer pitch after CMP planarization — achieving less than 1-micrometer bond pitch that no solder or epoxy could approach.