die attach
**Die Attach and Interconnection Technologies** are the **semiconductor packaging processes that physically and electrically connect bare dies to substrates, interposers, or other dies** — ranging from traditional wire bonding and solder bumps to advanced copper pillar micro-bumps and hybrid bonding, where the interconnect technology determines signal bandwidth, thermal dissipation, mechanical reliability, and the minimum achievable I/O pitch, with sub-10 µm pitch hybrid bonding enabling the tight integration required for chiplet architectures.
**Die Attach Methods**
| Method | Pitch | Bandwidth | Thermal | Application |
|--------|-------|-----------|---------|-------------|
| Wire bonding | 35-60 µm | Low | Good | Legacy, memory, sensors |
| C4 solder bump | 100-150 µm | Medium | Medium | Flip chip CPU/GPU |
| Cu pillar micro-bump | 40-55 µm | High | Good | 2.5D/3D, HBM |
| Hybrid bonding (Cu-Cu) | 1-10 µm | Very high | Excellent | Advanced 3D, SRAM-on-logic |
| Thermocompression (TCB) | 40-100 µm | High | Good | Fine-pitch flip chip |
**Solder Bump (C4) Process**
```
Step 1: Under Bump Metallurgy (UBM)
[Die pad (Al or Cu)] → [Ti/Cu/Ni barrier/seed] → [UBM provides wettable surface]
Step 2: Bump formation
- Electroplating: Cu pillar + SnAg solder cap
- Or: Stencil print solder paste → reflow
- Bump height: 50-100 µm
Step 3: Flux application
- No-clean flux applied to substrate pads
Step 4: Die placement
- Pick and place die face-down (flip chip) onto substrate
- Alignment: ±5-10 µm
Step 5: Reflow
- Heat to ~250°C → solder melts and self-aligns
- Intermetallic compound (IMC) forms at interface
Step 6: Underfill
- Epoxy dispensed between die and substrate
- Cures to provide mechanical support and CTE stress relief
```
**Thermocompression Bonding (TCB)**
- For fine-pitch Cu pillar bumps (<55 µm pitch).
- Bond head presses heated die onto heated substrate.
- Temperature: 250-350°C, pressure: 10-50 N, time: 1-3 seconds.
- Advantage: No mass reflow → adjacent bumps don't reflow → tighter pitch.
- Used for: HBM die stacking, 2.5D chiplet attachment.
**Hybrid Bonding (Cu-Cu Direct Bonding)**
```
[Die 1: Cu pads + SiO₂ surface] [Die 2: Cu pads + SiO₂ surface]
↓ Surface activation (plasma) + alignment ↓
[Oxide-oxide bond at room temperature] → [Cu-Cu bond at 300°C anneal]
Result: Direct metallic bond, no solder, no bump → pitch down to ~1 µm
```
- Pitch: 1-10 µm (vs. 40+ µm for micro-bumps).
- Bandwidth: >1 Tb/s/mm² (10-100× solder bumps).
- No underfill needed → thinner packages.
- Used in: Sony image sensors (pixel + logic stacking), TSMC SoIC.
**Comparison**
| Parameter | C4 Solder | Cu Pillar | Hybrid Bond |
|-----------|----------|-----------|-------------|
| Pitch | 100-200 µm | 40-55 µm | 1-10 µm |
| Pads/mm² | 25-100 | 330-625 | 10,000-1,000,000 |
| Contact R | ~10 mΩ | ~5 mΩ | ~0.1 mΩ |
| Process T | 250°C reflow | 250-350°C TCB | RT bond + 300°C anneal |
| Yield | Mature | Good | Improving |
**Reliability Considerations**
| Failure Mode | Mechanism | Prevention |
|-------------|-----------|------------|
| Solder joint fatigue | CTE mismatch → thermal cycling cracks | Underfill, compliant bump |
| Electromigration | High current density → void formation | Larger bumps, Cu pillar |
| IMC growth | Intermetallic thickening → brittle fracture | Low-T storage, Cu pillar |
| Kirkendall void | Unequal diffusion rates | Barrier layer optimization |
Die attach and interconnection technologies are **the physical links that determine the bandwidth and reliability of every semiconductor package** — the evolution from wire bonding to solder bumps to hybrid bonding represents a 1000× improvement in interconnect density, enabling the chiplet revolution where multiple dies are connected with bandwidth densities rivaling monolithic integration.