Diffused Base 1954 Define Device Mesa

# Define the Device Mesa: Carving Individual Transistors Out of a Wafer That Diffused Identically Everywhere

This step etches away the surrounding diffused material around each intended device, leaving small raised mesas that each carry their own complete emitter-base-collector sandwich — a necessary step because every diffusion since Step 11 was a blanket process, laid down uniformly across the entire wafer surface with no masking to distinguish one future device's location from another's. Steps 12 through 20 produced a wafer where every point carries an identical stack of junctions, which is exactly correct for a single device and exactly wrong for a wafer meant to yield many independent ones — without this step, every device on the wafer would share its base and emitter layers with every neighboring device, electrically connected to all of them at once.

## 1. Isolation Depth Has to Clear Both Junctions Without Touching the Collector Margin Underneath Them

$$x_{j,\text{base}} < d_{\text{mesa etch}} < t_{\text{wafer}} - t_{\text{collector,min}}$$

This step's etch depth $d_{\text{mesa etch}}$ has to exceed the base junction depth $x_{j,\text{base}}$ by enough margin to fully sever the base layer between adjacent devices — an etch that stops short of this leaves a thin, continuous base-type bridge still connecting neighboring mesas beneath the surface. At the same time, this depth cannot approach the wafer's remaining thickness closely enough to threaten the collector margin Step 6 originally budgeted and Step 10 confirmed survived, which means this step inherits a bounded target with the same shape as nearly every earlier dimensional decision in this sequence, now applied laterally between devices rather than vertically through one.

## 2. Real Diagram: A Blanket Diffusion Has No Device Boundaries Until This Step Cuts Them In

Before This Step, the Wafer Has No Device Boundaries at All every diffusion so far treated the whole surface as one continuous area base layer, continuous across the entire wafer emitter layer, continuous across the entire wafer this step's etch, cutting these boundaries in for the first time every device-to-device separation on the finished wafer is this step's work, not a byproduct of any earlier one

## 3. The Mesa Sidewall Exposes a New Surface No Earlier Step Ever Had to Protect

$$\text{sidewall junction exposure} \to \text{new leakage path, untreated by Steps 1 through 20}$$

Cutting through both junctions to isolate each device also exposes both junction edges at the mesa's sidewall, a surface this process never had to consider before this step existed, because every earlier operation worked on the wafer's flat top or bottom face. An exposed junction edge at a cut sidewall is a known leakage risk, structurally different from the planar junction area this process has spent twenty steps carefully diffusing — this step's etch quality, and whatever surface treatment follows it, determines whether that newly exposed edge behaves like the rest of the junction or becomes the finished device's weakest point.

Isolation Creates a Surface the Rest of This Process Never Protected twenty steps of careful planar diffusion did nothing to prepare for this exposed edge exposed junction edge, mesa sidewall this edge did not exist until this step's etch created it, and nothing earlier in the sequence was designed around it

## Define the Device Mesa's Place in the Process Lineage

Defining the device mesa is step twenty-one of Bell Labs' twenty-six-step diffused-base manufacturing sequence — immediately after the emitter drive-in finished setting the base width, and before any individual device is contacted or tested. It is the step that finally imposes device boundaries on a wafer whose diffusions have, until now, treated the entire surface as one continuous area, and it does so by cutting a depth bounded on one side by the base junction it has to clear and on the other by the collector margin it cannot afford to threaten. Step twenty-two, attaching the emitter lead, is the first step to treat this wafer as a collection of separate, individually addressable devices rather than one uniform surface.

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