digital simulation rtl

**Digital Simulation** is the **software-based evaluation of a circuit's logical behavior by stimulating inputs and observing outputs over time** — the primary verification method used at RTL, gate, and netlist levels throughout the chip design flow. **Simulation Levels** **RTL (Register Transfer Level) Simulation**: - Simulate Verilog/VHDL behavioral model. - Fastest — no cell delays, no routing parasities. - Used for: Functional verification, catching logical bugs. - Tools: Synopsys VCS, Cadence Xcelium (ncsim), Mentor ModelSim/Questa. **Gate-Level Simulation (GLS)**: - Simulate synthesized netlist with standard cell delays from SDF (Standard Delay Format). - SDF file: Back-annotated delays from timing analysis. - Catches: Functional failures that only occur due to actual cell delays (timing-dependent logic). - Catches X-propagation: Unknown values from reset sequences or uninitialized registers. - Slower than RTL simulation — up to 100x slower for complex designs. **Post-Layout Simulation**: - Full RC parasitics from PEX (parasitic extraction) back-annotated. - Most accurate but slowest. - Used for: Final functional verification before tapeout. **Testbench Architecture** - **DUT (Device Under Test)**: The design being simulated. - **Stimulus Generator**: Creates input sequences. - **Reference Model**: Golden model for comparison. - **Checker/Scoreboard**: Compares DUT output to reference — flags mismatches. - **Coverage Collector**: Measures what has been exercised. **UVM (Universal Verification Methodology)** - Industry standard for complex verification environments. - Reusable component libraries (agent, driver, monitor, scoreboard). - Randomized constrained testing + functional coverage. **Coverage Types** - **Code coverage**: Lines/branches/conditions exercised in RTL. - **Functional coverage**: User-defined events/scenarios exercised. - **Toggle coverage**: Every net toggles 0→1 and 1→0. Digital simulation is **the workhorse of chip verification** — designs receive millions of simulation cycles before tapeout, and achieving target coverage closure (typically > 95% code and functional coverage) is a prerequisite for chip release.