Active Area Etch

The active area etch — AA Etch or ACT Etch — cuts the diagonal lines of silicon that will eventually become every transistor's channel in the DRAM array, and the lines run diagonally rather than on-axis specifically because a tilted active area lets a single buried wordline cross two neighboring cells' active lines at the most space-efficient angle the 6F² cell layout allows. This etch takes the spacer-defined fine pitch from the SAQP sequence earlier in the flow and transfers it straight into silicon itself, which means every bit of CD control and sidewall quality the mandrel and spacer etches fought to achieve now has to survive one more etch step without degrading.

Running the active lines diagonally rather than parallel to the wordlines is a deliberate geometric trick that lets one buried wordline do double duty across two cells at once, which is the entire reason a 6F² cell can pack this densely in the first place. A straight, on-axis layout would force each wordline to serve only the cells directly in its own row; tilting the active area at an angle lets a single wordline trench cross two separate active lines on its way across the array, effectively sharing wordline real estate between neighboring cells — this geometric arrangement, decided purely by layout, is what the active area etch has to execute faithfully in silicon, angle and all.

Because this etch cuts a crystalline material rather than an amorphous dielectric, the plasma chemistry has to be tuned to respect the silicon crystal structure, not just hit a target depth. HBr/Cl2/O2-based chemistries dominate active silicon etching specifically because they offer the controllable balance of etch rate, sidewall passivation, and crystallographic selectivity silicon demands — an etch that works perfectly on an oxide hard mask can behave completely differently once it reaches the silicon underneath, which is why the active area etch's recipe gets qualified as its own distinct step even though it immediately follows a hard-mask transfer that used a related but different chemistry.

Sidewall angle in this etch directly becomes the transistor's own channel geometry, which is a much higher-stakes consequence than in most other hard-mask-protected etches. A slightly tapered or rounded active-line sidewall doesn't just look imperfect under inspection — it changes the effective channel width and the electric field distribution the eventual buried wordline gate will see, meaning any profile drift here propagates straight into cell-to-cell transistor variation the same way a buried-wordline-trench depth mismatch does; DRAM makers run this etch on the same high-aspect-ratio silicon etch platforms — Lam Research, Applied Materials, Tokyo Electron — tuned for the buried wordline trench itself, because both etches are fighting the identical underlying problem of holding silicon profile fidelity at extreme density.

Read the active area etch through a *layout-decided-the-angle* lens rather than a *just-another-silicon-etch* lens — the diagonal orientation isn't an etch artifact or a process quirk, it's a deliberate cell-density decision made at the layout stage, and this etch's entire job is faithfully executing that decided geometry in real silicon without letting the etch itself introduce any angle or profile error of its own.