Alignment Key Open
The alignment key open — called Key Open or Mark Open — clears a small, dedicated area of the wafer, usually outside the active cell array entirely, so the overlay and alignment marks underneath can stay visible to the exposure tool and the metrology system for every single layer still to come. Every one of the dozens of patterned layers in a DRAM flow has to line up with the layers already built beneath it, and that alignment is only possible if the lithography scanner and the overlay metrology tools can still actually see a reference mark through whatever film got deposited on top of it most recently — this etch's entire job is making sure they can.
A mark buried under too many layers of accumulated film eventually becomes invisible to the scanner no matter how carefully it was originally made, which is exactly the failure this etch exists to prevent. Each successive deposition without a corresponding key open adds optical path length and signal attenuation on top of the original mark, degrading contrast until the alignment system either reads the mark with reduced confidence or loses it entirely — a DRAM flow with dozens of patterned layers simply cannot afford to let any mark degrade that far, so key open gets scheduled deliberately through the process specifically to refresh mark visibility before it becomes a problem, not reactively after an alignment failure has already occurred.
This step is deliberately simple precisely because the mark area it protects carries no cell-array function of its own. The key open etch doesn't need the self-alignment tricks, aspect-ratio control, or material-matched depths that the cell module's real pattern-defining etches depend on — it just has to clear accumulated film cleanly over a dedicated reference region without mattering electrically, which is also why it's treated as a utility step scheduled across the flow wherever marks need refreshing rather than as a tightly integrated piece of any single module.
Losing a usable alignment mark has consequences that ripple through every subsequent layer, not just the one layer that failed to align. If a key open gets skipped or a mark degrades past the point of reliable use, the scanner either falls back to a different, possibly less accurate reference mark elsewhere on the wafer or the lot has to be reworked, and any layer that printed with compromised alignment carries that overlay error forward into everything built on top of it — which is why fabs track mark visibility as its own metric across a lot's full process history, not just at the specific layer where a problem might eventually surface.
Read the alignment key open through a *keeping-the-ruler-readable* lens rather than a *routine-housekeeping* lens — nothing about this etch builds a feature the chip will ever use, but every other etch in this entire DRAM flow depends on a scanner being able to see exactly where the layers beneath it already sit, and that visibility only survives as long as someone keeps clearing the film that keeps piling up on top of it.