Bump Etch Rdl
Every metal layer covered earlier in this project connects two adjacent structures that already sit at roughly the same pitch regime; the redistribution layer exists for a genuinely different purpose — translating between two deliberately different pitch requirements — and the bump etch that follows it opens the final sites where that translation ends in a physical solder or copper bump. TSVs sit at whatever tight pitch the die's internal routing and stacking density demand, often just tens of micrometers apart, but a mechanically reliable solder bump needs far more spacing than that to survive repeated thermal cycling without adjacent bumps bridging or cracking under stress, so the RDL fans conductor traces outward from each tightly-packed TSV tip to a much more widely spaced bump site, and the bump etch then opens access to each of those final, far-apart landing pads.
Pitch translation, not simple electrical connection, is the RDL's defining job, which makes it structurally unlike every prior metal layer in this entire sequence including the M1 trench and via etches covered earlier in the back end. M1 and the vias above it connect one metal layer to the next at a pitch that barely changes layer to layer, because their job is routing within a density regime that stays roughly constant; the RDL instead has to span from the TSV's dense native pitch out to a bump pitch that can be several times wider, which means its own metal lines run comparatively long distances across the die relative to the tight, short connections every earlier metal layer needed — a difference that shows up directly in RDL metal thickness, since longer fan-out traces need a thicker, lower-resistance conductor to keep IR drop and signal integrity acceptable over that extra routing distance.
Bump pitch, not etch resolution, is usually the binding constraint on how many TSVs a single die can expose through this interface, which inverts the density story this entire project has told from the front end onward. Every structure this sequence has covered, from the storage-node hole to the via etch, has been limited by how small and how dense a feature the etch technology itself could reliably form; the bump interface instead gets limited by a completely different physical requirement — how closely spaced two solder or copper-pillar bumps can sit before thermal and mechanical reliability degrades — which means a die's TSV count or arrangement sometimes has to be designed around the RDL's fan-out capability rather than around any etch process limitation, a rare case in this project where the bottleneck sits downstream of the etch sequence rather than inside it.
Read through a last-translation-before-the-handshake lens, the bump/RDL etch closes this project's original roadmap exactly where the whole sequence has been heading since the storage-node hole etch at the start: every structure covered has existed to make a reliable electrical connection somewhere on the die, and this final one makes the very last connection the entire chip will ever need before it meets another die, a substrate, or a package — the point where internal density finally has to translate into something physically bondable to the outside world.