DRAM scaling technology

**DRAM Scaling and High Bandwidth Memory** is **the continued evolution of dynamic random-access memory through aggressive cell scaling, 3D stacking, and high-speed interfaces — addressing the memory wall that limits processor performance by delivering bandwidth exceeding 1 TB/s through HBM technology while maintaining cost-effective density scaling through sub-20 nm DRAM process nodes**. **DRAM Cell Scaling:** - **Capacitor Challenge**: DRAM cell requires minimum ~10 fF storage capacitance for reliable sensing; as cell area shrinks below 0.003 μm², maintaining capacitance requires extreme aspect ratios (>60:1) in capacitor structures - **High-k Dielectrics**: ZrO₂/Al₂O₃/ZrO₂ (ZAZ) stacks with effective k > 40 replace traditional SiO₂/Si₃N₄; enables sufficient capacitance in smaller footprint; atomic layer deposition (ALD) provides conformal coating on high-aspect-ratio structures - **Buried Word Line**: transistor gate buried below silicon surface reduces cell height and improves electrostatic control; saddle-fin channel structure provides adequate drive current at sub-20 nm half-pitch - **EUV Adoption**: DRAM manufacturers (Samsung, SK Hynix, Micron) adopting EUV lithography at 1α (14-15 nm) and 1β (12-13 nm) nodes; reduces multi-patterning complexity for critical layers **High Bandwidth Memory (HBM):** - **Architecture**: vertically stacked DRAM dies (8-12 layers) connected by through-silicon vias (TSVs); wide I/O interface (1024-bit bus width) delivers massive bandwidth; base logic die handles interface and ECC - **HBM3/HBM3E**: 8-12 die stacks delivering 460-1200 GB/s per stack; 16-36 GB capacity per stack; 3.2-9.6 Gbps per pin data rate; power efficiency ~3-5 pJ/bit - **TSV Integration**: ~5000+ TSVs per die connecting stacked layers; TSV diameter ~5-6 μm with ~40 μm pitch; micro-bump bonding between dies at ~40 μm pitch; hybrid bonding emerging for next-generation HBM - **AI Accelerator Demand**: NVIDIA H100 uses 5× HBM3 stacks (80 GB, 3.35 TB/s); H200 uses HBM3E (141 GB, 4.8 TB/s); B200 uses 8× HBM3E stacks (192 GB, 8 TB/s); HBM demand driven almost entirely by AI training and inference **DDR5 and LPDDR5:** - **DDR5**: 4800-8400 MT/s data rates; dual 32-bit channels per DIMM (vs single 64-bit in DDR4); on-die ECC corrects single-bit errors before data leaves the DRAM chip; 1.1V operating voltage - **LPDDR5/5X**: 6400-8533 MT/s for mobile and automotive; 16-bit channel architecture; deep sleep mode <5 mW; LPDDR5X used in flagship smartphones and automotive ADAS systems - **CXL Memory**: Compute Express Link enables memory expansion beyond DIMM slots; CXL-attached DRAM provides pooled memory with ~200 ns additional latency; enables terabyte-scale memory for AI and HPC workloads - **Processing-in-Memory (PIM)**: embedding compute logic within DRAM arrays; Samsung HBM-PIM adds SIMD units to HBM base die; reduces data movement energy for AI inference by 70% **Scaling Outlook:** - **Node Roadmap**: 1γ (sub-12 nm) and 1δ (sub-10 nm) DRAM nodes in development; each node provides ~20% bit density improvement; physical limits of capacitor scaling approaching within 3-4 nodes - **3D DRAM**: vertical channel DRAM (analogous to 3D NAND) being researched; stacking capacitor cells vertically could extend DRAM scaling beyond planar limits; Samsung, SK Hynix demonstrating prototypes - **Alternative Memories**: MRAM, ReRAM, and ferroelectric RAM offer non-volatility but cannot match DRAM density and cost; DRAM remains dominant for main memory through at least 2030 - **Bandwidth Scaling**: HBM4 targeting >2 TB/s per stack with hybrid bonding; bandwidth growth outpacing capacity growth reflecting AI workload requirements DRAM scaling and HBM technology are **the critical memory innovations powering the AI revolution — without the massive bandwidth delivered by HBM stacks and the continued density improvements of advanced DRAM nodes, the computational potential of modern AI accelerators would be fundamentally bottlenecked by memory access limitations**.