dram technology scaling

**DRAM Technology and Scaling** is the **semiconductor memory technology that stores each bit as charge on a capacitor accessed through a transistor (1T1C cell) — where continued scaling requires solving the dual challenge of maintaining sufficient cell capacitance (>10 fF) in an ever-shrinking footprint while reducing refresh power, driving the industry toward high-aspect-ratio capacitors exceeding 100:1, advanced dielectric materials, and novel cell architectures**. **The 1T1C Cell** Each DRAM cell consists of one access transistor and one storage capacitor. The capacitor stores charge representing a "1" or "0." The access transistor connects the capacitor to the bitline for read/write. Sensing requires the stored charge to produce a detectable voltage on the highly-capacitive bitline — demanding a minimum storage capacitance regardless of cell size. **Capacitor Scaling Challenge** C = ε₀ × εᵣ × A / d, where A is the electrode area, d is the dielectric thickness, and εᵣ is the relative permittivity. As cell area shrinks, capacitance must be maintained by: - **Increasing height**: Capacitors are now 3D cylinders or pillars with aspect ratios >100:1. At the 1α (14nm) node, DRAM capacitors are ~4 μm tall in a cell pitch of ~30 nm — extreme aspect ratio etching and ALD deposition challenges. - **Increasing εᵣ**: Migration from SiO₂ (εᵣ≈4) → Al₂O₃ (εᵣ≈9) → ZrO₂/HfO₂ (εᵣ≈25-40) → ZAZ (ZrO₂/Al₂O₃/ZrO₂) stacks. Next generation: rutile TiO₂ (εᵣ>80) and perovskites. - **Reducing d**: Dielectric thickness is already ~3-5 nm. Further thinning increases leakage current, which drains the stored charge and forces more frequent refresh. **Cell Architecture Evolution** - **8F² Cell**: Traditional DRAM cell layout with 8F² area (F = feature size). Staggered bitline contacts. Standard through DDR4 era. - **6F² Cell**: Saddle-fin or buried channel transistor. Used by Samsung and SK Hynix for advanced DDR4/DDR5 nodes. Reduces cell area by 25% but requires more complex fabrication. - **4F² Cell**: Vertical channel transistor aligned with the bitline-wordline crossing. Each cell occupies the minimum possible area. Requires vertical surround-gate transistor with channel along the capacitor pillar. Under development for future DRAM nodes. **Refresh and Reliability** - **Refresh Rate**: Standard DRAM refreshes every 64 ms. At advanced nodes, increased leakage from thinner dielectrics and shorter retention time require more frequent refresh — consuming 30-40% of memory bandwidth in some workloads. - **Row Hammer**: Repeated activation of one DRAM row causes charge leakage in adjacent rows, flipping bits. Mitigations: target row refresh (TRR), increased refresh rates, and ECC. Row hammer vulnerability increases with denser cell pitch. DRAM Technology is **the critical memory scaling challenge that directly limits system performance for AI, HPC, and mobile computing** — where the physics of storing electrons in ever-smaller capacitors defines the boundaries of what memory systems can deliver.