semiconductor memory sram dram

**Semiconductor Memory Technologies** are **the diverse family of integrated circuit storage devices — from volatile SRAM and DRAM that lose data when power is removed, to non-volatile Flash and emerging memories that retain data indefinitely — each optimized for different combinations of speed, density, endurance, and cost that define the memory hierarchy from processor cache to mass storage**. **SRAM (Static RAM):** - **6T Bitcell**: two cross-coupled inverters form bistable latch, two access transistors connect to bitlines — data retained as long as power is applied; no refresh required; read by sensing differential voltage on complementary bitlines - **Performance**: fastest memory technology — access time 0.5-2 ns; used for L1/L2/L3 caches where speed is critical; operates at full processor clock frequency - **Area Penalty**: 6T cell is 100-150× larger than DRAM cell — typical bitcell area: 0.02-0.05 μm² at 7nm node; limits practical SRAM capacity to tens of megabytes on-chip - **Design Challenges**: read stability (noise margin), write ability, and hold margin must be simultaneously optimized — cell ratio (pull-down/access transistor ratio) and pull-up ratio determine read/write margins; process variation in minimum-size transistors limits yield **DRAM (Dynamic RAM):** - **1T1C Cell**: single access transistor and storage capacitor — charge on capacitor represents stored bit; capacitor charge leaks through transistor sub-threshold current requiring periodic refresh (every 32-64 ms) - **Capacitor Scaling**: maintaining >20 fF capacitance as cells shrink below 20 nm pitch — high-k dielectrics (ZrO₂/Al₂O₃/HfO₂ stack), 3D capacitor structures (pillar or cylinder) with aspect ratios >60:1 - **Refresh Overhead**: each row must be periodically read and rewritten — refresh consumes 10-30% of DRAM bandwidth and power; Row Hammer vulnerability: repeated access to one row disturbs adjacent rows requiring mitigation (TRR, PARA) - **HBM (High Bandwidth Memory)**: 3D-stacked DRAM with TSVs providing >1 TB/s bandwidth — 4-16 die stack with wide (1024-bit) interface; bonded to logic die or silicon interposer; essential for AI accelerators **Non-Volatile Memory:** - **NAND Flash**: floating gate or charge trap transistors store data as threshold voltage levels — SLC (1 bit/cell), MLC (2), TLC (3), QLC (4 bits/cell); 3D NAND stacks 100-300 layers vertically for density; program/erase endurance 1K-100K cycles depending on technology - **NOR Flash**: random-access read capability at near-DRAM speed — used for code storage (boot ROM) in embedded systems; lower density than NAND but enables execute-in-place (XIP) operation - **MRAM (Magnetoresistive RAM)**: magnetic tunnel junction stores data as parallel/anti-parallel magnetization — non-volatile, unlimited endurance, SRAM-comparable speed; becoming embedded replacement for SRAM/Flash in MCUs - **ReRAM/PCRAM**: resistive switching (filament formation/dissolution) or phase change (crystalline/amorphous) — positioned between DRAM and Flash in the memory hierarchy; Intel Optane used PCRAM before discontinuation **Semiconductor memory technologies collectively form the multi-level memory hierarchy that bridges the enormous speed gap between processors and storage — understanding the fundamental tradeoffs between speed, density, volatility, endurance, and cost is essential for system architects designing the memory subsystems of modern computing platforms.**