Wl Cap Etch Back
The WL cap etch-back planarizes a nitride capping layer deposited over the finished buried wordline fill, removing it down to a controlled depth that seals the metal or poly gate inside the trench beneath a protective nitride plug rather than leaving it exposed at the silicon surface. Everything the trench etch, the saddle fin recess, the metal recess, and the poly recess accomplished inside that trench is only useful if the gate stays electrically isolated from whatever gets built directly on top of it next — the cap etch-back is what actually closes the trench back up after all of that careful internal geometry work is finished.
This cap's top surface has to end up flush with, or at a precisely controlled relationship to, the surrounding active silicon surface, because the very next module in the flow — the bitline contact — depends on a predictable surface topography to self-align correctly. A cap that sits too high leaves a step the bitline contact etch has to clear through extra material it wasn't expecting; a cap that recesses too low can expose more of the gate or surrounding structure than the isolation was designed to allow, so this etch-back is tuned as carefully to its target surface height as the earlier STI oxide recess was to its own datum, because both are setting up the geometry the next module takes for granted.
This planarization also has to be uniform across every trench on the wafer simultaneously, which is the same pattern-density challenge every other wafer-wide etch in this flow faces. A nitride cap sitting above a dense array of narrow buried-wordline trenches doesn't necessarily clear at the same rate as any isolated or wider test structure used to qualify the recipe, so this etch-back has to be characterized directly against the real cell-array pattern density rather than against a simplified blanket film, which is why it's typically developed as part of the same process window study that qualifies the WL metal and poly recess steps feeding into it.
High-aspect-ratio dielectric etch and CMP platforms handle this step depending on whether the integration scheme favors a dry etch-back or a polish-based planarization. Some DRAM makers etch the cap back with a timed or endpoint-controlled plasma process on the same tool families used for the trench etch itself — Lam Research and Applied Materials among them — while others integrate a CMP step to achieve the flatness this surface needs before the bitline contact module begins; which approach a given process generation uses depends on exactly how tight the surface-height tolerance the bitline contact's self-alignment can tolerate turns out to be.
Read the WL cap etch-back through a *closing-the-trench-cleanly* lens rather than a *just-planarizing* lens — every careful internal structure this buried wordline module built gets protected or wasted depending entirely on how precisely this one closing step leaves the surface, because the next module in the flow inherits that surface as a given rather than something it checks for itself.