DRAM 64k 1979 Full Row Activation Refresh Coupling

# One Strobe Touches Every Cell in a Row, Whether You Asked It To or Not

## 1. Follow RAS Past Addressing Into What It Actually Does to the Array

Step 2 treated $\overline{RAS}$ as an addressing signal: it tells the chip which pins to latch as a row address. That description is accurate but incomplete in a way this step must correct before the series goes further. Asserting $\overline{RAS}$ does not merely *record* a row address somewhere for later use — it physically activates every access transistor along the selected row simultaneously, connecting every one of that row's storage capacitors to its own bit line at once. The row this project's lineage has, since 1968, always discussed as "the row a cell belongs to" turns out to be a hardware-enforced unit of operation, not just an addressing convenience: you cannot activate one cell in a row without activating all of them.

$$\text{assert }\overline{RAS}\implies\forall j\in\text{row } i:\ \text{cell}(i,j)\text{ connects to bit line}_j$$

This single fact — that row activation is inherently plural — is the mechanism Step 2's $t_{RAS,min}$ timing bound was actually governing: every one of those simultaneously activated cells needs its own sense amplifier to resolve its own bit line's small charge-sharing signal, and $t_{RAS,min}$ is the time the slowest of those many simultaneous resolutions needs, not the time any single cell's resolution would take alone.

RAS Activates an Entire Row of Cells, Not One the addressing signal from Step 2 is simultaneously a hardware activation signal RAS line → cell(i,0) cell(i,1) cell(i,2) cell(i,3) cell(i,j) ONE STROBE, EVERY CELL IN THE ROW, SIMULTANEOUSLY you cannot activate cell(i,2) alone — asserting RAS activates the whole row t_RAS,min is set by the SLOWEST of all these simultaneous sense-amp resolutions a side effect follows directly from this plurality every cell in the row gets refreshed too, whether you wanted that or not — Section 2

## 2. Recognize the Unasked-For Side Effect: Every Access Refreshes a Whole Row

The 1968 series established that a DRAM cell's stored charge leaks and must be periodically refreshed before it decays past the sense amplifier's reliable detection threshold — $t_{ret}\approx C_sV_{dd}/I_{leak}$, a per-cell retention clock this project has carried through every DRAM series since. Reading a cell, in the 1968 series' original single-cell framing, restores that cell's charge as a byproduct of the sense amplifier doing its job. Section 1 of this step shows that single-cell framing was never quite literal: reading *one* cell at address $(i,j)$ via this multiplexed addressing scheme necessarily activates and re-senses every other cell in row $i$ as well, restoring all of their charge in the same operation.

$$\text{access}(i,j)\implies \text{refresh}(i,0),\text{refresh}(i,1),\ldots,\text{refresh}(i,n-1)$$

This is not a bug introduced by address multiplexing — it was already true of row-organized arrays before multiplexing existed — but this series' $\overline{RAS}$ mechanism makes the row-wide activation an explicit, controllable signal for the first time, rather than an implicit property buried inside the array's physical layout. A system designer can now assert $\overline{RAS}$ alone, without ever following it with $\overline{CAS}$, purely to refresh an entire row's worth of cells at once, without caring which specific column would otherwise be selected.

RAS Alone Becomes a Deliberate Row-Refresh Tool Real Diagram — a single address access refreshes an entire row as a side effect NORMAL ACCESS: RAS + CAS RAS activates whole row i CAS selects column j within it every cell in row i gets refreshed as a byproduct, not the stated intent RAS-ONLY REFRESH CYCLE RAS asserted, CAS never follows entire row refreshed, column irrelevant cycle through every row address refreshes the full array systematically access(i,j) ⟹ refresh(i,0), refresh(i,1), ..., refresh(i,n−1) 1968's per-cell retention clock now has an entire row satisfied in one stroke this is the mechanism the next step's refresh strategy exploits directly how many RAS-only cycles does a full refresh need? a direct function of array geometry — Step 4

## 3. Place Row-Wide Refresh in the DRAM Lineage, and Name the Next Dependency

This step reveals the deepest connection this series has made yet to the project's earlier DRAM work. The 1968 series derived retention time per cell in isolation, treating refresh as a property each cell needed individually. The 1974 series optimized how much charge a single cell's capacitor could hold against that same retention clock. Neither series needed to ask how refresh would actually be *performed* across an entire array of millions of cells, because neither series had yet built the addressing mechanism — row-organized, multiplexed, strobe-controlled — that this series is assembling. This step is the first point where this project's DRAM lineage connects the physics of why a cell needs refreshing (1968, 1974) to the *mechanism* by which an entire array of cells actually gets refreshed in practice (this series).

The practical consequence this step leaves for Step 4 is direct: since one $\overline{RAS}$-only cycle refreshes an entire row, refreshing the whole 64K array requires only as many cycles as there are rows — not as many cycles as there are cells. Step 4 takes up that count explicitly: how the array's row-versus-column geometry is chosen, what number of refresh cycles per retention interval that geometry implies, and what fraction of the chip's total available access time a systematic refresh schedule built on this row-wide mechanism actually consumes.

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