DRAM Scaling 1974 Build the Trench Etch Depth Area Budget

# Step 3 — Build the Trench: Etch Depth as the New Area Budget

## 1. Sidewall Area Replaces Planar Pitch

By cutting a high-aspect-ratio vertical cavity into the silicon substrate with reactive-ion etching, the trench capacitor converts depth into the memory cell's new surface-area budget. In the classic planar 1T1C cell established in 1968, the capacitor’s surface area was locked to the cell’s horizontal footprint ($A \approx F^2$). When lithographic scaling shrinks the minimum feature size $F$, a flat plate’s area falls quadratically, starving the bit line of charge. The trench capacitor breaks this thermodynamic scaling limit by wrapping the capacitor plates around the vertical perimeter of an etched hole:

$$A_{\text{trench}} = \pi \cdot d \cdot d_{\text{etch}} + \frac{\pi d^2}{4} \approx \pi \cdot d \cdot d_{\text{etch}}$$

where $d$ is the trench opening diameter ($\approx F$) and $d_{\text{etch}}$ is the etch depth into the bulk substrate ($3\text{ to }8\ \mu\text{m}$). The resulting storage capacitance becomes:

$$C_s = \frac{\varepsilon_{\text{di}} A_{\text{trench}}}{t_{\text{di}}} \approx \frac{\varepsilon_{\text{di}} (\pi \cdot d \cdot d_{\text{etch}})}{t_{\text{di}}}$$

Capacitance now scales linearly with depth $d_{\text{etch}}$, completely decoupled from planar cell pitch. If lithography cuts the lateral feature size in half ($d \to d/2$), the memory designer can maintain a constant signal charge ($C_s \ge 35\ \text{fF}$) simply by etching twice as deep into the silicon. The physical limit of DRAM scaling shifts from lithographic printing resolution to plasma etch depth.

Building the Trench: Etch Depth as Area Budget converting horizontal cell area into a vertical sidewall perimeter-depth product DEEP SUBSTRATE TRENCH ARCHITECTURE WL Gate Buried N⁺ Plate N⁺ Poly Storage Node Buried Strap Diameter d ≈ 0.5 µm Depth h = 6–8 µm THE GEOMETRIC MULTIPLICATION FACTOR 1968 Planar Baseline Area (d = 0.5 µm): Aplanar = πd² / 4 = 0.196 µm² → Cs ≈ 3.5 fF (Unviable!) 1974+ Deep Trench Sidewall Area (h = 6 µm): Atrench ≈ π · d · h = 9.42 µm² Area Multiplication Factor: 9.42 / 0.196 > 48× Gain Recovered Signal Charge: Cs ≈ 38 fF → Reliable ΔV = 200 mV sense margin Top of wafer remains completely flat for lithography. THE PHYSICAL PAYOFF OF THE TRENCH ARCHITECTURE ✓ 48× Capacitance Gain: Achieved without increasing the horizontal silicon footprint of the memory cell ✓ Planar Lithography Retained: Zero step height above the wafer protects depth-of-focus for word-line and bit-line patterning The area crisis is solved in the Z-axis, but a new manufacturing constraint emerges: Aspect Ratio Limits.

## 2. The New Constraint: Aspect Ratio Limits and RIE Lag

Leaving the plane trades lithographic area limits for high-aspect-ratio plasma etching limits. As diameter $d$ contracts and depth $h$ expands, the aspect ratio ($\text{AR} = h / d$) rapidly climbs past $10:1$ and toward $20:1$, introducing three distinct physical failure mechanisms.

Aspect Ratio Constraints: RIE Lag, Bowing, and Keyhole Voids the three process failure modes that replace planar area limits in deep trench fabrication 1. RIE LAG / TRANSPORT BOTTLENECK CF₄ / SF₆ / O₂ Reactive Plasma Ions Knudsen Diffusion Limit Radicals deplete down hole Etch rate drops with depth (Lag) Aspect-Ratio Dependent Etching (ARDE) • Deep holes etch slower than wide test structures • Sidewall charge deflection causes bowing and tapering • Microtrenching at floor creates stress fractures 2. PINCH-OFF & KEYHOLE VOID FAILURE Pinch-off neck! KEYHOLE VOID Conformal Deposition Breakdown • Poly overhang at trench mouth seals before bottom fills • Trapped void reduces effective capacitance unpredictably • Corrosive etch byproducts trapped in void cause reliability flaws The New Engineering Boundary: The trench capacitor escapes the 2D planar lithography limit, but binds the fab to aspect ratio control and conformal CVD filling.

## 3. Place This Step in the Project's Own Lineage

Step 3 introduces the first concrete implementation of 3D charge storage, establishing how vertical manufacturing redefines the governing parameters of the cell:
1. The Circuit Invariance of 1968 Maintained: The circuit operation remains identical to Robert Dennard’s 1968 1T1C baseline. The access transistor still gates charge into a storage node. But while 1968 treated capacitance as an unproblematic two-dimensional sheet ($C = \varepsilon A / t_{ox}$), Step 3 reveals that the area term $A$ must become a vertical sidewall cylinder ($A \approx \pi d \cdot d_{\text{etch}}$) to survive sub-micron scaling.
2. Replacing One Physical Constraint with Another: Planar scaling died because light and dielectric breakdown constrained lateral area and oxide thickness. The trench capacitor evades both, but immediately encounters the fluid and plasma dynamics of high-aspect-ratio holes: Knudsen diffusion throttling, aspect-ratio-dependent etching (ARDE), and keyhole void pinch-off.
3. Setting Up the Alternative Architecture: The trench capacitor chose to accept these difficult etching and void-free filling challenges specifically to keep the top of the wafer completely flat for optical lithography. Step 4 will explore the opposing philosophy: the stacked capacitor, which rejects deep substrate etching and instead builds upward into the sky above the transistor.

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