dual damascene

The damascene process exists because you cannot plasma-etch copper the way you etch aluminum. Copper has no stable, volatile etch byproduct at reasonable temperatures, so the old subtractive scheme of depositing a metal blanket and etching the wires out of it simply does not work for copper. Damascene flips the order: you pattern the trenches and vias into the dielectric first, then fill them with copper and polish the excess away. The name comes from the ancient inlay technique of setting metal into carved channels, which is exactly what the process does at nanometer scale.\n\n**Every damascene wire is built by inlay, not by carving.** The dielectric is etched to form the trench that will become a wire and the via that will connect down to the layer below. That patterned dielectric is the mold. Copper is then deposited to overfill the mold, and chemical-mechanical planarization grinds everything back flat so that copper remains only inside the recesses. What is left is a wire sitting in a dielectric channel, coplanar with its surroundings, ready for the next layer to be built on top.\n\n**The fill is a three-material stack, and each layer is a different tool.** First a barrier such as tantalum nitride goes down by PVD or ALD to stop copper from diffusing into the silicon and poisoning devices. Then a thin copper seed layer is sputtered on to carry plating current. Finally the bulk copper is grown by electroplating, which fills the feature from the bottom up using organic additives that suppress deposition at the top and accelerate it at the bottom, avoiding voids. This is why PVD, electroplating, and CMP all show up as separate steps in a single wiring level.\n\n**Dual damascene forms the via and the trench in one copper fill.** Rather than filling the via, polishing, then filling the trench separately, a dual-damascene flow patterns both the via and the overlying trench into the dielectric and fills them together in a single plating-and-polish cycle. This roughly halves the number of copper deposition and CMP steps per layer. The two common orderings, via-first and trench-first, differ in which feature is etched before the other, trading lithography and etch complexity against each other.\n\n**Damascene is what made copper interconnect and low-k dielectrics possible together.** Because the copper never has to be etched, it can be paired with fragile low-k dielectrics that would not survive metal etch, and the barrier keeps the two apart. The cost is process complexity and the CMP-induced dishing and erosion that limit how wide a wire can be before its top sags during polish. Damascene is therefore inseparable from the CMP, plating, and barrier steps that surround it.\n\n| Aspect | Subtractive (aluminum) | Damascene (copper) |\n|---|---|---|\n| Order of operations | Deposit metal, then etch wires | Etch dielectric mold, then fill metal |\n| How the metal is shaped | Plasma etch of the metal | Electroplate fill + CMP polish |\n| Why | Al etches to volatile byproducts | Cu has no clean etch, so inlay instead |\n| Enables | Older aluminum interconnect | Copper + low-k, dual damascene |\n| Key surrounding steps | Metal etch, gap-fill dielectric | Barrier/seed PVD, ECP plating, CMP |\n\n```svg\n\n```\n\nRead damascene through an inlay-because-copper-cannot-be-etched lens rather than a generic patterning lens. The instant you accept that copper has no clean etch, the entire flow is forced: you must carve the dielectric, line it against diffusion, plate the metal in from the bottom, and polish it flat, which is why damascene drags PVD barriers, electroplating, and CMP along with it as one inseparable wiring recipe.