damascene process
The damascene process exists because copper cannot be plasma-etched. Aluminium forms volatile AlCl₃ at room temperature in a chlorine plasma, so for decades the interconnect wiring scheme was subtractive: deposit a metal blanket, pattern photoresist on top, etch the unmasked metal away, and fill the gaps with dielectric. Copper changed everything. It forms no volatile halide below roughly 200 °C, and the non-volatile copper chloride residue that remains after a plasma strike is hygroscopic, corrosive, and impossible to clean. The industry's solution, introduced by IBM at the 220 nm node in 1997, was to invert the order of operations: etch trenches and vias into the dielectric first, line them with a diffusion barrier, fill them with electroplated copper, and polish the overburden away with CMP. The metal never has to be etched; instead it is inlaid into a pre-carved mold, exactly as a medieval metalworker in Damascus would set gold wire into an engraved steel blade. This is the damascene process, and every copper interconnect layer built in the last quarter-century — from the thickest redistribution line on a 2.5D interposer to the tightest M1 wire at the 2 nm node — uses some variant of it.
**The fundamental reason for damascene is that copper has no clean etch product.** In a chlorine or bromine plasma the reaction $\text{Cu} + \text{Cl}_2 \to \text{CuCl}_2$ produces a solid with a vapour pressure below $10^{-6}$ Torr at 100 °C, far too low to volatilise during a practical etch step. By contrast, aluminium etching produces $\text{AlCl}_3$ with a vapour pressure exceeding 1 Torr at the same temperature, which is why subtractive Al patterning worked for decades. Without a volatile by-product, any attempt to plasma-etch copper leaves a rough, corroded residue that shorts adjacent lines and poisons downstream processes. Damascene eliminates the metal-etch problem entirely by never exposing the copper surface to a patterning plasma.
**Single damascene and dual damascene differ in how many metal features are filled per CMP cycle.** In single damascene, the via and the trench are formed and filled in separate process sequences: the via is etched into the dielectric, filled with copper, and polished flat; then the trench is etched into a second dielectric layer deposited on top, filled with copper, and polished again. This requires two complete barrier–seed–plate–CMP cycles per interconnect level. Dual damascene combines the via and trench into a single dielectric stack: both features are etched before any metal deposition, then barrier, seed, and copper fill are applied once, and a single CMP step removes the overburden. Dual damascene roughly halves the number of deposition and CMP steps per metal level, reducing cost and cycle time, but demands more complex lithography and etch because two features of different depth must be defined in one dielectric layer without damaging the other.
**The via-first integration scheme etches the via before the trench, which is the most widely used dual-damascene flow.** The sequence begins by depositing a dielectric stack — typically a cap layer (SiCN or SiN), the inter-layer dielectric (ILD, a low-k material such as SiOCH), and an optional hard mask. Via lithography defines the via pattern, which is etched through the full dielectric thickness down to an etch-stop layer (ESL) that protects the underlying metal. The via is then partially filled with organic planarising material (OPL) to protect its bottom during the subsequent trench etch. Trench lithography defines the wire pattern, and a timed trench etch removes the upper portion of the dielectric to the target trench depth. The OPL is stripped, the ESL at the via bottom is opened with a gentle breakthrough etch, and the dual-damascene mold is complete and ready for metallisation.
**The trench-first integration scheme etches the trench before the via, offering simpler via lithography at the cost of more complex trench-depth control.** In this flow, the trench pattern is lithographically defined and etched to a controlled depth (a timed etch, since there is no etch-stop layer within the dielectric for the trench), then the via pattern is lithographed into the trench floor and etched through the remaining dielectric to the ESL below. The advantage is that the via lithography takes place on a relatively flat surface (the trench floor) rather than on a topographic step, improving CD control. The disadvantage is that the timed trench etch must hit its target depth within a tight tolerance (typically ±5% of the trench depth) across the wafer, because there is no material contrast to stop on.
**The barrier layer is the containment wall that prevents copper from poisoning the transistors.** Copper diffuses rapidly through silicon dioxide and low-k dielectrics at temperatures as low as 200 °C, and a single copper atom reaching the silicon channel degrades minority-carrier lifetime and shifts threshold voltage. The barrier must therefore be continuous, conformal, and pinhole-free on the trench and via sidewalls and bottom. The industry-standard barrier is a tantalum nitride (TaN) / tantalum (Ta) bilayer deposited by ionised PVD (iPVD): the TaN layer (1–3 nm at advanced nodes) provides the diffusion barrier, and the Ta layer (1–2 nm) provides a wetting surface for the copper seed. At the 5 nm node and below, atomic-layer-deposited (ALD) TaN is replacing PVD TaN on the sidewalls because iPVD cannot achieve adequate conformality in features with aspect ratios exceeding 8:1.
**The copper seed layer carries the plating current and nucleates the electroplated film.** A thin copper film (20–60 nm) is sputtered by iPVD onto the barrier, covering all surfaces of the trench and via. The seed must be continuous on the sidewalls and bottom — any break in coverage creates a void during electroplating because the plating solution cannot deliver current to an electrically isolated region. At aggressive aspect ratios (above 5:1), the seed on the lower sidewall thins to a few nanometres, approaching the percolation threshold where the film becomes discontinuous. Techniques to extend seed continuity include high-power impulse magnetron sputtering (HiPIMS) for more directional deposition, substrate bias to resputter seed from the bottom to the sidewall, and two-step seed processes with a thin ALD copper or cobalt wetting layer underneath the PVD seed.
**Electrochemical plating (ECP) fills the damascene mold from the bottom up using a cocktail of organic additives.** The plating bath is an acidified copper sulphate solution ($\text{CuSO}_4$ at 30–60 g/L Cu²⁺, $\text{H}_2\text{SO}_4$ at 5–10 g/L, HCl at 30–70 ppm) supplemented with three classes of organic additives: an accelerator (typically bis-(3-sulphopropyl) disulphide, SPS, at 2–10 ppm), a suppressor (a polyethylene glycol, PEG, at 50–300 ppm), and a leveller (Janus Green B or a proprietary nitrogen-bearing polymer, at 1–5 ppm). The accelerator adsorbs preferentially at the via bottom and catalyses fast copper deposition there; the suppressor adsorbs on flat surfaces and the trench opening, retarding deposition at the top; the leveller further inhibits deposition at protruding features. The combined action of all three additives creates a deposition-rate gradient that fills the feature from the bottom up, eliminating the pinch-off voids that would form if deposition were uniform on all surfaces.
**The superfill mechanism depends on the area-reduction effect.** As the feature fills from the bottom, the surface area at the bottom decreases while the concentration of accelerator per unit area increases — the adsorbed accelerator molecules are compressed into a shrinking area. This positive feedback accelerates the bottom deposition rate further, creating the concave fill front that is the hallmark of void-free electroplating. The curvature-enhanced accelerator concentration (CEAC) model, developed by Josell, Wheeler, and Moffat at NIST, quantitatively predicts this behaviour by tracking the local surface coverage of accelerator as the fill front advances. When the feature aspect ratio exceeds approximately 5:1, the additive cocktail must be retuned (higher accelerator, lower suppressor) to maintain bottom-up fill, and at aspect ratios above 10:1, conventional ECP begins to fail and alternative fill methods such as electroless plating or CVD copper are considered.
**Post-plating anneal is mandatory to transform the as-plated copper microstructure.** As-deposited electroplated copper has a fine-grained, highly twinned microstructure with a resistivity 20–30% higher than bulk copper (1.68 µΩ·cm at 20 °C). A thermal anneal at 150–400 °C for 30 seconds to several minutes drives recrystallisation and grain growth, converting the fine grains into large "bamboo" grains that span the full width of the interconnect line. This grain growth reduces resistivity to within 5–10% of bulk copper and eliminates the stress built up during plating. At the same time, self-annealing — a room-temperature recrystallisation process that occurs over hours to days in as-plated films — must be controlled by performing the intentional anneal promptly after plating, before uncontrolled self-annealing degrades wafer-to-wafer uniformity.
**The etch-stop layer (ESL) at the bottom of each dielectric layer is what makes the dual-damascene via etch self-stopping.** The ESL — typically silicon carbon nitride (SiCN, 5–15 nm) or silicon nitride (SiN) — sits on top of the lower copper line and serves two functions: it prevents copper diffusion upward into the dielectric, and it provides a material-contrast endpoint for the via etch. The etch chemistry for the low-k dielectric (fluorocarbon-based: CF₄, C₄F₈, or C₄F₆ with O₂ and Ar) etches the dielectric rapidly but stops on the ESL with selectivity exceeding 10:1. After the trench etch is complete, a short breakthrough etch (using CH₂F₂ or CHF₃) removes the ESL at the via bottom to expose the underlying copper. The ESL open is a critical step: too aggressive an etch damages the copper surface and degrades via resistance; too gentle an etch leaves ESL residue that increases via contact resistance.
**Low-k dielectric integration is the companion challenge to damascene metallisation at every new node.** The RC delay of an interconnect wire is proportional to the product of its resistance ($R \propto \rho L / A$, where $\rho$ is metal resistivity, $L$ is wire length, and $A$ is cross-sectional area) and its capacitance ($C \propto k \varepsilon_0 A_{\text{cap}} / d$, where $k$ is the dielectric constant and $d$ is the spacing between wires). Reducing $k$ below the SiO₂ value of 3.9–4.2 requires introducing porosity or carbon into the dielectric matrix: SiOCH (CDO) achieves $k$ = 2.5–3.0, and porous SiOCH achieves $k$ = 2.0–2.5. But each reduction in $k$ weakens the dielectric mechanically — Young's modulus drops from 72 GPa (SiO₂) to 3–8 GPa (porous low-k) — making the film vulnerable to cracking during CMP, delamination at interfaces, and moisture uptake that raises $k$ back toward 4.
**Copper resistivity scaling is the fundamental limit that is pushing damascene toward alternative metals.** In bulk copper, the resistivity is 1.68 µΩ·cm at 20 °C. But in a narrow damascene line, electron scattering at the grain boundaries (Mayadas–Shatzkes model) and at the barrier/copper interfaces (Fuchs–Sondheimer model) raises the effective resistivity. At a line width of 20 nm, the effective copper resistivity is approximately 4–5 µΩ·cm — nearly 3× the bulk value. The barrier layer, which occupies a fixed 2–5 nm on each side of the trench, further reduces the available copper cross-section: in a 20 nm trench with 3 nm barrier on each side, only 14 nm is copper, meaning the barrier consumes 30% of the line width. These two effects — grain-boundary and surface scattering plus barrier occupation — combine to make the resistance of narrow copper lines increase much faster than simple geometric scaling would predict.
**Electromigration reliability in damascene copper is governed by the cap interface, not the bulk metal.** In aluminium interconnects, electromigration (atom transport driven by electron wind at high current density) proceeds primarily along grain boundaries, and the bamboo grain structure that develops in narrow lines slows the process. In damascene copper, the bamboo grains that form after anneal effectively block grain-boundary diffusion, but the interface between the copper surface and the dielectric cap layer (SiCN or SiN, deposited after CMP) becomes the dominant diffusion path. The activation energy for cap-interface diffusion is only 0.7–0.9 eV, compared to 1.1 eV for grain-boundary diffusion and 2.1 eV for lattice diffusion. Improving electromigration lifetime therefore requires either a better cap–copper interface (achieved by selective cobalt cap, CuSiN treatment, or self-assembled monolayer adhesion promoters) or a switch to metals like cobalt or ruthenium whose oxide interfaces are more resistant to atomic migration.
**The cap layer deposited after CMP seals the copper and prevents oxidation during subsequent processing.** After the CMP buff step, the exposed copper surface is chemically reactive and will oxidise rapidly in air, forming CuO and Cu₂O that degrade via resistance and promote delamination. A thin (10–30 nm) SiCN or SiN cap is deposited by PECVD within minutes of the CMP clean, hermetically sealing the copper. This cap also serves as the etch-stop layer for the next via level, completing the cycle: the cap of layer N is the ESL of layer N+1. At advanced nodes, selective cobalt (Co) or cobalt tungsten phosphide (CoWP) caps are deposited by electroless plating on the copper surface only — not on the dielectric — providing a stronger adhesion and a higher electromigration activation energy (0.9–1.2 eV) than SiCN.
**Semi-damascene is an emerging integration scheme that combines subtractive metal patterning with damascene gap fill.** Announced by Intel for the 18A (1.8 nm equivalent) node and beyond, semi-damascene etches the metal lines subtractively (using a hard mask and an aggressive metal etch or ion-beam etch) and then fills the gaps between lines with dielectric, followed by CMP. This approach is feasible for metals like ruthenium and molybdenum that can be dry-etched with acceptable profiles, unlike copper. The advantage is that the metal line can be deposited as a thick blanket with large grains and no barrier needed if the metal is self-barrier (Ru, Mo), eliminating the barrier-occupation problem. The disadvantage is the return of gap-fill challenges for the dielectric and the need for high-selectivity metal-etch processes that do not damage the adjacent dielectric.
**Alternative metals — cobalt, ruthenium, and molybdenum — are being introduced at the tightest pitches where copper's resistivity penalty is worst.** At line widths below 15 nm, the effective resistivity of copper inside a TaN/Ta-lined trench exceeds 6 µΩ·cm, while cobalt (bulk 6.2 µΩ·cm) or ruthenium (bulk 7.1 µΩ·cm) deposited without a barrier can fill the full trench cross-section and deliver comparable or lower total line resistance. Cobalt has been adopted for contact-level wiring (M0, via-0) at the 7 nm and 5 nm nodes by several foundries, deposited by CVD from Co₂(CO)₈ precursors and reflowed at 300–400 °C to fill the via. Ruthenium is under development for M1 and M2 levels, where its etchability and self-barrier properties make semi-damascene integration feasible. Molybdenum is being explored for buried power rails, where its low resistivity (5.3 µΩ·cm bulk) and compatibility with subtractive etch offer advantages over copper in high-aspect-ratio trenches that are difficult to fill by ECP.
**The post-CMP clean sequence is as critical as the polish itself because slurry residue degrades reliability.** After CMP, the wafer surface retains abrasive particles (colloidal silica, 20–80 nm), organic slurry additives, dissolved copper ions, and corrosion inhibitor (BTA) residue. If not removed, these contaminants cause via resistance tails, dielectric leakage, and time-dependent dielectric breakdown (TDDB). The clean sequence typically proceeds as: dilute HF dip (removes surface oxide and embedded particles), megasonic rinse (dislodges particles using cavitation at 0.8–1.5 MHz), brush scrub with dilute citric acid (chelates copper ions), and a final DI water rinse and spin dry. At advanced nodes, the clean budget is constrained by the fragility of the porous low-k dielectric — aggressive cleans that strip carbon from the pore surfaces raise the effective $k$ and increase line-to-line capacitance.
**Dummy fill (also called tile insertion) is a design-level compensation for CMP pattern-density effects.** CMP removal rate depends on the local pattern density of metal within the slurry contact area (typically a few mm²). Isolated wide metal lines experience higher local pressure and faster removal (dishing), while dense arrays erode the dielectric between lines. To equalise the effective pattern density, EDA tools insert electrically inert metal tiles into empty regions of each metal layer, bringing the local density to a target window (typically 30–70%). These dummy features are not connected to any circuit node and must be spaced far enough from active wires to avoid coupling capacitance. The pattern-density specification is a DFM (design for manufacturability) rule that flows backward from the CMP process window into the physical design tool.
**Barrier-first versus liner-first process ordering determines whether the barrier or the wetting liner contacts the dielectric.** In the standard TaN/Ta bilayer, TaN goes down first (barrier-first): TaN provides the diffusion barrier against copper migration, and Ta provides a body-centred-cubic template that promotes strong (111)-textured copper growth during the seed step. An alternative approach reverses the order (liner-first), depositing a thin Ru or Co liner directly on the dielectric for adhesion, followed by ALD TaN for the barrier and then the Cu seed. The liner-first scheme improves adhesion at the dielectric interface and allows the TaN to be thinner (sub-1 nm) because it no longer needs to carry the mechanical adhesion function. This is relevant at the 3 nm node and below, where every angstrom of barrier thickness directly subtracts from the conducting copper volume.
**Dishing and erosion are the CMP-induced planarisation defects inherent to the damascene flow.** Because the copper is softer than the surrounding dielectric, CMP preferentially over-polishes the metal, causing wide lines to recess below the dielectric surface (dishing) and dense arrays to thin uniformly (erosion). These effects are not bugs — they are fundamental consequences of the selectivity mismatch between copper and oxide in the slurry. Managing them requires stiffer pads, optimised slurry selectivity, controlled over-polish time, and dummy-fill insertion at the design level to equalise effective pattern density across the die.
**The dielectric etch for damascene must produce vertical sidewalls with minimal bowing and no etch-stop damage.** The trench and via profiles directly determine the electrical characteristics of the finished wire: a tapered trench increases capacitance between adjacent lines; a bowed trench reduces the effective cross-section and increases resistance; undercut at the hard-mask interface creates a void-prone overhang. The etch chemistry — typically a fluorocarbon gas (C₄F₈ or C₄F₆) mixed with O₂ and Ar at low pressure (10–30 mTorr) — must be tuned to deposit a thin fluorocarbon polymer on the sidewall during etching, protecting the sidewall from lateral attack while the ion-driven vertical etch proceeds. For porous low-k dielectrics, the etch must also avoid depleting the methyl groups (-CH₃) from the exposed pore surfaces, which would raise the effective dielectric constant and negate the benefit of using low-k in the first place. Post-etch pore sealing with a thin plasma-deposited SiCN or PECVD oxide restores the hydrophobic surface chemistry.
**The hierarchy of metal levels in a modern logic chip follows a dimensional pyramid.** The tightest-pitch wires at the bottom (M1, M2) carry local signals between adjacent transistors, with line widths as small as 12–16 nm and aspect ratios of 2–3:1. The intermediate levels (M3–M6) carry semi-global signals at slightly relaxed pitch. The upper levels (M7–M14+) carry power and global signals with line widths of 100–1,000 nm and much lower aspect ratios. Each tier uses the same damascene integration but with different process parameters: the bottom levels use the most aggressive barrier/seed/fill chemistry, the tightest litho overlay, and the most sensitive endpoint detection; the upper levels are more forgiving but require thicker copper fills and longer CMP times. This metal-level hierarchy means that a single chip may execute 30–50 damascene sequences, each tuned to a different dimensional regime.
```flowchart
Dual-Damascene Process Flow (Via-First)
Start: ILD deposited on capped Metal N-1
│
▼
Deposit hard mask (SiO₂ / TiN)
│
▼
Via lithography (define via pattern)
│
▼
Via etch through ILD to ESL (SiCN)
── selectivity: ILD:ESL > 10:1
│
▼
Fill via with OPL (organic planarising layer)
── protects via bottom during trench etch
│
▼
Trench lithography (define wire pattern)
│
▼
Timed trench etch (partial ILD depth)
── target depth ±5% uniformity
│
▼
Strip OPL + ESL breakthrough etch
── expose Metal N-1 copper at via bottom
│
▼
Degas + preclean (Ar sputter clean)
── remove Cu oxide from via bottom
│
▼
Barrier PVD: TaN (1–3 nm) + Ta (1–2 nm)
── or ALD TaN for AR > 8:1
│
▼
Cu seed PVD (20–60 nm iPVD)
── continuous sidewall coverage critical
│
▼
Cu ECP fill (SPS + PEG + leveller)
── bottom-up superfill, 300–800 nm overburden
│
▼
Post-plate anneal (150–400°C)
── grain growth, resistivity reduction
│
▼
CMP 3-step (bulk Cu → barrier → buff)
── endpoint: eddy current + motor torque
│
▼
Post-CMP clean (brush + megasonic + dHF)
│
▼
Cap deposition: SiCN (10–30 nm) by PECVD
── seals Cu, becomes ESL for next level
│
▼
Ready for next ILD → repeat for Metal N+1
```
**The most common professional mistake in damascene integration is treating the barrier as electrically invisible.** A process engineer who models the resistance of a 20 nm copper line using the bulk copper resistivity of 1.68 µΩ·cm will under-predict the actual resistance by a factor of 3–4, because the barrier consumes 30% of the available cross-section and grain-boundary scattering raises the effective copper resistivity to 4–5 µΩ·cm. The correct approach is to compute the effective resistivity using the Mayadas–Shatzkes model for grain-boundary scattering, the Fuchs–Sondheimer model for surface scattering, and then reduce the effective conducting area by twice the barrier thickness on each side. At narrow dimensions, this compound effect is why cobalt and ruthenium — despite having bulk resistivities 3–4× higher than copper — can deliver lower line resistance: they require no barrier layer, so the full line cross-section conducts.
**Time-dependent dielectric breakdown (TDDB) in low-k dielectrics is the reliability limit most directly tied to damascene process quality.** Copper ions that escape through a defective barrier migrate through the dielectric under the operating electric field, eventually forming a conductive filament that shorts adjacent lines. The time to breakdown depends exponentially on the barrier integrity, the copper ion concentration in the dielectric, the operating temperature, and the line-to-line spacing. At the 5 nm node, the minimum line spacing is 12–14 nm and the electric field across the low-k dielectric exceeds 1 MV/cm, placing extreme demands on barrier continuity. A single pinhole in the TaN barrier can reduce the TDDB lifetime from 10 years to days, which is why barrier deposition is the most defect-sensitive step in the entire damascene sequence.
**Dual-damascene lithography overlay must be tighter than the via diameter to avoid via-to-line misalignment.** If the via pattern is misregistered relative to the trench, the via will partially land on the dielectric instead of fully contacting the underlying copper line, creating a high-resistance or open connection. At the 3 nm node, via diameters are approximately 12–15 nm and the overlay budget is 2–3 nm (3σ), requiring EUV lithography for both the via and trench layers. The transition from ArF immersion (193 nm) to EUV (13.5 nm) for BEOL lithography was driven primarily by the overlay requirements of dual-damascene integration at tight pitches, not by resolution alone.
**Airgap integration replaces the low-k dielectric between wires with empty space to achieve the lowest possible capacitance.** After forming the copper wires by standard damascene, the dielectric between adjacent lines is selectively etched away (using dilute HF or a vapour-phase etch that attacks the ILD but stops on the barrier and cap), leaving an air gap with an effective $k$ approaching 1.0. A thin non-conformal dielectric is then deposited on top to seal the gaps without filling them. Air-gap integration has been used at the 14 nm and 10 nm nodes by some foundries for the tightest-pitch metal levels, reducing line-to-line capacitance by 20–30% compared to porous low-k. The trade-off is mechanical fragility: the unsupported copper lines are vulnerable to deformation during CMP of subsequent layers, and the sealed cavity can trap moisture if the seal is imperfect.
| Aspect | Subtractive Al | Single Damascene Cu | Dual Damascene Cu | Semi-Damascene (Ru/Mo) |
|---|---|---|---|---|
| Metal patterning | Plasma etch of Al blanket | N/A (Cu filled into dielectric mold) | N/A (Cu filled into dielectric mold) | Subtractive etch of Ru or Mo blanket |
| Dielectric patterning | Gap fill after metal etch | Via etch, fill, CMP; then trench etch, fill, CMP | Via + trench etched together, single fill and CMP | Gap fill after metal etch |
| Barrier required | None (Al is self-barrier) | TaN/Ta bilayer on all surfaces | TaN/Ta bilayer on all surfaces | None (Ru, Mo are self-barrier) |
| CMP steps per level | One (dielectric planarisation) | Two (one per feature) | One (single Cu + barrier CMP) | One (dielectric planarisation) |
| Key advantage | Simple, mature | Via and trench independently optimised | Fewest process steps per level | No barrier occupation, large-grain metal |
| Key disadvantage | Cu cannot be etched this way | Double the CMP and plate cycles | Complex dual-feature etch and litho | Dielectric gap fill, metal etch damage |
| Typical nodes | 250 nm and above (1990s) | Early Cu nodes (180–130 nm) | 130 nm to present | 18A (1.8 nm equivalent) and beyond |
Read damascene through an *inlay-because-copper-cannot-be-etched* lens rather than a *generic-wiring* lens: every step in the flow — dielectric etch, barrier deposition, seed sputtering, electroplating, anneal, CMP, cap deposition — exists because copper has no volatile etch product, so the metal must be inlaid into a pre-carved mold rather than subtractively patterned. The canonical example — a 20 nm trench with 3 nm TaN/Ta barrier, 30 nm Cu seed, bottom-up ECP fill with SPS/PEG/leveller at pH 0.5, 250°C anneal, three-step CMP with eddy-current endpoint, SiCN cap — changes its resistance, reliability, and yield if any one of these variables drifts, because the barrier thickness sets the conducting area, the seed continuity determines whether voids form, the additive chemistry determines whether the fill is bottom-up or conformal, the anneal determines the grain structure, the CMP determines the dishing, and the cap determines the electromigration lifetime. Every hard problem in damascene is a different way of asking: how thin can the barrier be while still blocking diffusion, and how small can the feature be while still filling void-free?