via

A via (from the Latin "via" meaning road or way) is a vertical electrical connection that passes through one or more dielectric layers to connect metal interconnect lines on different levels in a semiconductor integrated circuit. Vias are essential structural elements in multilayer metallization schemes, enabling complex three-dimensional routing of signals, power, and ground connections throughout the chip. In the dual damascene process flow used at advanced nodes, vias are formed by etching cylindrical holes through the inter-metal dielectric (IMD), depositing a barrier/liner layer (typically Ta/TaN), and filling with copper using electrochemical deposition (ECD), followed by chemical-mechanical planarization (CMP) to remove excess metal. Via dimensions have scaled aggressively with each technology node — at the 3 nm node, via diameters are approximately 15-20 nm, creating extreme aspect ratios that challenge both lithographic patterning and metal fill processes. Key reliability concerns for vias include electromigration, stress migration, and via resistance. Via resistance increases rapidly as dimensions shrink due to electron scattering from grain boundaries and sidewalls, making barrier thickness optimization and metal fill quality critical. Via placement and density also significantly impact timing and signal integrity in the interconnect network. Multi-patterning or EUV lithography is required to pattern vias at the tightest pitches of advanced nodes. Self-aligned via (SAV) technology, where the via is lithographically defined but its final position is determined by the adjacent metal line topography, has been adopted at leading-edge nodes to relax overlay requirements. Buried power rail architectures at future nodes place power delivery vias beneath the transistors through the silicon substrate, representing a paradigm shift in via integration. Via arrays and redundant vias are commonly used in design rules to improve yield and electromigration reliability.