Dual-Stage Lithography Scanner

A dual-stage lithography scanner runs two wafer stages instead of one, so a wafer can be measured and leveled on one stage while a different wafer is actually being exposed on the other. ASML's TWINSCAN system popularized this architecture in the early 2000s and it has since become the standard design for high-volume DUV and EUV scanners — the stages swap positions between the measurement station and the exposure station once each cycle finishes.

Wafer A on measurement stage
Alignment marks, leveling, height map
Wafer B on exposure stage
Scanning exposure in progress
Stage swap cycleBoth operations run concurrently, then stages trade places
Measurement completes
Full height/alignment map ready before swap
Exposure completes
Full field set exposed on current wafer
Stage swap
Measured wafer moves to exposure position
↻ next wafer pair
Exposed wafer unloads
New wafer loads onto now-empty measurement stage

The swap hides the measurement time almost entirely. On a single-stage scanner, every wafer has to be measured, then exposed, in sequence — the exposure optics sit idle during the whole measurement step. With two stages, the measurement of the *next* wafer happens in parallel with the exposure of the *current* one, so the only idle time on the expensive exposure optics is the brief mechanical swap itself. For a tool whose optics represent the majority of its cost, that's the difference between exposure-limited throughput and measurement-limited throughput.

Dual-Stage Scanner — Measure and Expose in Parallel two stages trade places so the exposure optics are almost never idle Measurement station wafer A alignment + leveling scan Exposure station wafer B scanning exposure, slit by slit stages swap once both operations finish single-stage: measure → expose → measure → expose (serial) dual-stage: measure(next) ‖ expose(current), then swap this is the architecture ASML's TWINSCAN introduced and every modern DUV/EUV scanner now uses

The measurement itself got more demanding at the same time the parallel architecture arrived, which is no coincidence. As feature sizes shrank, overlay budgets tightened to the point where a single alignment reading per wafer wasn't enough — scanners now build a dense height and alignment map across dozens of sites per wafer before exposure even starts. That richer measurement step would have crushed throughput on a single-stage design; the dual-stage architecture is what made it affordable to measure that thoroughly without giving up wafers-per-hour.

The dual-stage scanner is one of those architectural decisions that looks like pure mechanical cleverness but is really a throughput argument: by the early 2000s, exposure optics and measurement precision had both become too valuable to leave idle, and running two stages was the only way to keep both busy at once.

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