dynamic

**Dynamic Logic and Domino CMOS Design** is **asynchronous-input-free logic families using precharged nodes and conditional discharge — enabling faster circuits than static CMOS at the cost of complex timing and power considerations**. Dynamic logic uses precharged evaluation nodes rather than always-on pull-up/pull-down paths. Precharge phase charges node to V_dd via PMOS. Evaluate phase conditionally discharges through NMOS stack. If stack conducts, node discharges to ground; otherwise remains at V_dd. Output switches based on final voltage. Domino logic cascades dynamic stages. Precharge discharges are propagated through stages like falling dominoes. Single clock phase (evaluate) enables rapid stage transitions. Speed advantages: dynamic stages are faster than static CMOS due to:1) single-transistor pull-down (vs series stack), 2) pre-discharged nodes have shorter transition distance, 3) cascading between stages requires no static inversion overhead. Performance improvement 30-50% vs static. Clock distribution: dual-clock (precharge, evaluate) required. Non-overlapping clocks essential — both transistors conducting simultaneously causes shoot-through current. Careful timing ensures safe operation. Power supply noise impacts: precharged nodes sensitive to noise. Noise during precharge phase alters final charge. Voltage ripple on supply couples into nodes. Higher switching current and power consumption than static logic. Heat generation and thermal effects more severe. Cascaded logic depth: cascading multiple domino stages improves speed. Each stage operates in single evaluate phase. Long chains may overflow to next clock cycle, limiting benefits. Careful pipelining optimizes depth. Keeper device: weak cross-coupled keeper transistor holds charged node during metastable conditions. Prevents node collapse from noise. Adds complexity. Leakage: precharge devices must be sized properly. Weak precharge slow but saves power. Strong precharge fast but wastes power. Optimization balances competing goals. Monotone logic: some logic functions (AND, OR, NAND, NOR) naturally monotone. XOR/XNOR are problematic — inverters introduce dependencies. Complex logic requires careful gate design. Noise margins: dynamic nodes have no static full-voltage pull-up. Noise immunity less than static logic. Careful design maintains margins. Clock skew sensitivity: dynamic logic sensitive to clock skew. Early evaluate discharges node prematurely. Late precharge leaves node discharged. Tight clock skew control essential. Hybrid designs: static/dynamic mixing enables exploiting dynamic speed where beneficial, static stability elsewhere. Transitions at domain boundaries require careful design. Latch-up and noise: dynamic logic more susceptible to latch-up due to large transient currents. Guard rings and substrate biasing mitigate. **Dynamic logic provides speed advantage over static CMOS through precharged evaluation, requiring complex clock distribution, careful timing, and robust noise management.**