eco design

**ECO (Engineering Change Order)** — a late-stage modification to a chip design after tapeout or during production, typically using only metal layer changes to fix bugs without re-spinning the entire chip. **Types** - **Pre-tapeout ECO**: Logic change made to netlist/layout before manufacturing. Full flexibility - **Metal-only ECO**: Change only metal layers (wiring) — reuse existing transistor masks. Saves 6-8 weeks vs full re-spin - **Metal-and-via ECO**: Slightly more flexibility than metal-only **How Metal ECO Works** 1. Identify the bug (simulation, formal verification, or silicon debug) 2. Synthesize a logic fix using spare cells (pre-placed unused gates) 3. Route new connections using only metal layers 4. Re-manufacture only the 8-12 metal masks (vs. 60+ total masks) **Spare Cells** - Designers scatter unused gates (NAND, NOR, DFF) across the chip before initial tapeout - ECO logic is built from these spare cells - Typically 2-5% of total gate count reserved as spares **Cost Impact** - Full re-spin at 3nm: $300-500M+ in mask costs alone - Metal-only ECO: $50-100M (still expensive but much less) - Time savings: 2-3 months faster to corrected silicon **ECOs** are the "patch" mechanism for silicon — every complex chip has a plan for metal-fix capability.