timing closure

**Timing Closure and ECO** is the **iterative removal of setup and hold timing violations via incremental design modifications — cell upsizing, buffer insertion, logic restructuring, floorplan adjustment — typically requiring 5-10 iterations and completing weeks before tapeout — essential for achieving first-pass silicon success**. Timing closure is the final gate to tapeout. **Setup and Hold Violations** Setup timing: data must arrive at flip-flop input before clock edge (setup time, t_su). Slack = (clock_arrival) - (data_arrival + t_su). If slack < 0, setup violation. Violation causes data metastability or incorrectness. Setup is worst at slow corners (SS, low voltage, high temperature). Hold timing: data must remain stable for hold time after clock edge. Slack = (data_departure) - (clock_departure + t_hold). If slack < 0, hold violation. Hold is worst at fast corners (FF). Modern timing analysis checks both simultaneously (multi-corner STA), reporting worst slack across all corners and violations. **Iterative Setup Violation Fixing** Fixing setup violation (delay too large): (1) identify critical path (longest delay), (2) reduce delay by: (a) upsizing cells (larger transistor drive, reduce gate delay), (b) inserting buffers (split large capacitive load, reduce delay), (c) logic restructuring (reorder gates, alternative logic, reduce levels), (d) floorplan adjustment (move blocks closer, reduce interconnect delay), (e) adjust clock tree (add clock skew, useful-skew CTS). Iteration: (1) fix most critical path, (2) re-run STA, (3) identify new critical path, (4) repeat. Typical 5-10 iterations required; each iteration finds less-critical violations (marginal improvements). Final iteration converges when all violations closed with sufficient margin. **Hold Fix via Buffer Insertion** Fixing hold violation (data arrives too early): (1) identify hold-critical path (short delay, needs to be slower), (2) increase delay by inserting buffers (add stage delay), (3) upsize cells not helpful (faster). Buffer insertion is selective: buffers added only on fast paths (leave slow paths unchanged, preserving setup margin). Balancing setup and hold: some paths are setup-critical (delay needs to be reduced), others are hold-critical (delay needs to be increased). One path cannot be both; design balances trade-off via selective cell sizing and buffer insertion. **ECO (Engineering Change Order)** ECO is a formal process for post-layout design changes: (1) request ECO (identify violation, propose fix), (2) analyze impact (does fix break other constraints?), (3) implement change (modify layout, schematic), (4) verify fix (re-run STA, check new violations), (5) approve ECO (sign-off by design and verification team). ECO is used for: (1) logic changes (rewire gates, change logic function), (2) placement changes (move cells closer), (3) layer changes (use different metal layer, better routability), (4) spare cell additions (prepopulate spare cells, activate via metal-only ECO for yield improvement). **Spare Cell ECO** To avoid full re-implementation late in design (expensive, long turnaround), spare cells are added during initial design. Spare cells: (1) prepopulated in unused rows (placeholder cells), (2) isolated (not connected to logic), (3) if ECO needed, spare cells are activated (metal routing added to connect into logic, metal-only ECO). Metal-only ECO: (1) geometry unchanged (no impact on physical design), (2) only metal routing added (fast, 1-2 days turnaround), (3) low risk (minimal verification impact). Spare cell density: ~2-5% of total cells reserved (balances coverage vs area overhead). **Metal-Only ECO** Metal-only ECO modifies only metal layers (not cell layout, not transistors). Advantages: (1) fast turnaround (metal can be modified in days vs weeks for full re-layout), (2) low risk (cell transistor physics unchanged), (3) no impact on physical design (placement, routing of other cells unchanged). Limitations: (1) only fixes logic (rewire nets via metal), cannot fix leakage or timing of transistors themselves, (2) limited by spare cell availability (can only activate pre-placed spares), (3) area constrained (metal routability, must fit new routes in existing metal space). Metal-only ECO is preferred; full ECO reserved for critical changes. **Incremental STA After Each Change** After each ECO, STA is re-run on modified design: (1) extract modified netlist, (2) re-extract parasitics (if layout changed), (3) run STA at all corners, (4) check timing. Incremental STA tools (Primetime, Tempus) are faster than full STA (optimize for changed regions only), enabling quick turnaround. Typical STA run time: full-chip ~30-60 min, incremental ~5-10 min. Incremental STA is essential for iteration speed. **Signoff Timing with SI and POCV** Final STA (sign-off) includes: (1) signal integrity (SI) — crosstalk between signals, couples noise into path, adds delay, (2) POCV (parametric on-chip variation) — spatially-aware process variation derating, tighter than simple OCV. SI and POCV are slower to compute than basic STA (full-chip SI SPICE simulation hours to days), so are run selectively on critical paths (not whole chip typically). Sign-off STA combines: basic STA on full chip, detailed STA (SI + POCV) on critical paths. **Timing Closure Metrics** Design tracks timing closure progress: (1) number of violations (target: zero), (2) worst slack (target: >0 mV setup, >0 mV hold across all corners), (3) timing margin (target: >50 mV combined setup+hold), (4) path distribution (percentage of paths with slack > margin). Weekly status: design team reports progress (violations decreasing, slack improving, ETA to closure). Late-stage delays: if closure not achieved 2-3 weeks before tapeout, may require: (1) extended closure time (delay tapeout), (2) relaxed performance targets (lower frequency), (3) scope reduction (disable features), (4) post-si fixes (silicon fixes via metal ECO after tapeout). **Summary** Timing closure is a disciplined, iterative process essential for silicon success. Continued advances in incremental optimization tools and predictive sign-off enable tighter margins and faster closure.