setup violation fix

**Setup and Hold Violation Fixing** is the **engineering process of iteratively modifying a placed-and-routed netlist to resolve timing violations** — using cell resizing, buffer insertion, logic restructuring, and routing changes to achieve timing closure. **Setup Violation Causes and Fixes** **Setup Violation** (path too slow — data arrives after clock captures): - **Cell Sizing (Upsizing)**: Replace slow cell with faster (larger, more drive strength) variant. - Example: BUF_X1 → BUF_X4 — reduces delay by 30–50%. - Cost: Higher leakage, more area. - **Logical Restructuring**: Balance logic depth — move gates from late paths to early paths. - **Fanout Reduction**: High-fanout net → slow. Clone driver or insert buffer tree. - **VT Swapping**: HVT → LVT cell — lower threshold = faster switching. - Cost: Higher leakage. - **Net Route Optimization**: Shorten critical net by re-routing closer, widening wire. - **Duty Cycle / DCD**: Adjust clock waveform if timing skew is helping a competing path. **Hold Violation Causes and Fixes** **Hold Violation** (data arrives too early — violates minimum hold time): - **Buffer Insertion**: Insert delay cells (tie delay cells, BUF_X1) on violating path. - Must add exactly enough delay to satisfy hold without creating setup violation. - **Cell Downsizing**: Smaller cell → slower → more hold margin. - **High-VT Insertion**: HVT cells are slower → hold margin improvement. **Timing ECO (Engineering Change Order) Flow** 1. STA identifies violating paths (WNS, TNS). 2. ECO tool (Conformal ECO, StarRC) suggests fixes. 3. Fixes inserted incrementally without full re-place-and-route. 4. Re-run STA to verify fixes don't introduce new violations. 5. Re-run DRC/LVS on ECO changes. **Setup-Hold Interaction** - Fixing setup by upsizing can create hold violations on the same path. - Fixing hold by adding delay can worsen setup on tight paths. - Must optimize simultaneously — iterative convergence. **Physical Awareness** - Logic fix must be physically implementable in available white space. - ECO swap: Must fit within cell height, same site grid, no DRC violation. Timing violation fixing is **the critical skill separating successful tapeouts from failed ones** — systematic, PVT-aware timing closure determines whether a chip functions at its target frequency after fabrication.