Hold Time
Hold time is the minimum amount of time a signal must stay stable at a flip-flop's input AFTER the clock edge, and it's the mirror image of setup time, which requires that same signal to be stable BEFORE the clock edge. Together they define a forbidden window around every clock edge — violate either one, and the flip-flop can capture the wrong value or enter an undefined, unstable state that has nothing to do with the logic being wrong.
Hold time exists because a real flip-flop doesn't capture its input instantaneously — it takes a small but nonzero amount of time to actually latch the value after the clock edge arrives. Internally, the clock edge triggers an electronic process (opening and closing internal transfer gates, or switching internal latches) that needs the input to remain unchanged while that process completes. If the input changes too soon after the clock edge — before that internal capture has fully resolved — the flip-flop might end up partway between capturing the old value and the new one, with no guarantee which one it settles on.
Hold time and setup time together define a single forbidden window of instability around every clock edge, and a design is only correct if every signal avoids that whole window. Setup time protects the period before the edge; hold time protects the period after it. A signal is only safe to change outside both windows — well before the edge, or safely after hold time has elapsed. Static timing analysis tools check every single path in a chip against both constraints simultaneously, because a design that satisfies setup time everywhere but violates hold time even on one path can still fail in silicon.
Hold-time violations are uniquely dangerous because, unlike setup violations, they usually can't be fixed by slowing the clock down. A setup violation means a signal arrived too late relative to the next clock edge — running the chip at a lower clock frequency, giving signals more time to propagate, generally fixes it. A hold violation means a signal changed too early relative to the SAME clock edge that just captured it, which is a race condition between two paths clocked by nearly the same edge; no amount of slowing the clock down helps, because the problem has nothing to do with how far apart the clock edges are. The only real fixes are adding deliberate delay to the offending path or restructuring the logic so the race doesn't exist in the first place.
Clock skew is the most common root cause of hold-time trouble, because it changes how close together two related clock edges effectively are. If a chip's clock signal arrives at two different flip-flops at slightly different times — because of wire-length differences, buffer-insertion differences, or process variation across the die — a fast downstream path can receive a new value before the receiving flip-flop's hold-time window (measured relative to its own, possibly-delayed clock edge) has closed. This is why clock-tree design treats skew as a serious hold-time risk, not just a setup-time or clock-quality concern, and why some high-speed designs deliberately insert small delays on short paths purely to guarantee hold-time margin.
Hold-time margin becomes a genuine physical design constraint once a chip reaches advanced process nodes, because the margins involved shrink to picoseconds while process variation doesn't shrink proportionally. A register-to-register path that's only a few gates long can easily violate hold time if it's simply "too fast" relative to the clock-tree delay feeding its two endpoints. Physical design tools routinely insert hold-time "filler" buffers — cells that do nothing logically except add a deliberate, small, well-characterized delay — purely to push a too-fast path's arrival time safely past the hold-time boundary. Getting this wrong at the margin a modern node requires is one of the quieter but most failure-prone parts of chip signoff, precisely because a hold violation can silently pass functional simulation and only show up as an intermittent failure once the chip is manufactured and running at real-world temperature and voltage variation.