energy efficiency hpc
**Energy Efficiency in HPC** is the **optimization of scientific and data-intensive computing systems to maximize useful computation per unit of energy consumed**, driven by the reality that power and cooling costs now dominate HPC facility budgets — an exascale system consumes 20-30 MW ($20-30M/year in electricity alone) — and that energy constraints, not transistor counts, limit the achievable performance of future systems.
The Green500 list ranks supercomputers by GFLOPS/watt rather than peak GFLOPS, reflecting the industry's recognition that energy efficiency is as important as raw performance. The most energy-efficient systems achieve 50-70 GFLOPS/watt, while the least efficient achieve <5 GFLOPS/watt — a 10x efficiency gap at similar performance levels.
**Power Breakdown in HPC Systems**:
| Component | Power Share | Optimization Lever |
|-----------|-----------|-------------------|
| **Compute (CPU/GPU)** | 40-60% | DVFS, power capping, accelerators |
| **Memory (DRAM/HBM)** | 15-25% | Data locality, compression, sleep |
| **Network** | 5-15% | Topology-aware placement, adaptive routing |
| **Cooling** | 20-40% (overhead) | Liquid cooling, free cooling, PUE optimization |
| **Storage** | 5-10% | Tiered storage, burst buffers |
**Dynamic Voltage and Frequency Scaling (DVFS)**: CPU/GPU power scales as P ∝ V^2 * f (and V ∝ f for digital circuits, so P ∝ f^3 approximately). Reducing frequency by 20% may reduce power by 50% while reducing performance by only 20% — a net energy efficiency gain. **Power capping** enforces a maximum power draw per node, letting the hardware optimize voltage/frequency within the cap. For communication-bound phases (where CPUs wait for MPI messages), DVFS can reduce CPU power significantly with minimal performance impact.
**Accelerator Efficiency**: GPUs achieve 10-50x better GFLOPS/watt than CPUs for suitable workloads because their massively parallel architecture amortizes control and memory overhead across thousands of threads. Specialized accelerators (Google TPUs, Cerebras WSE, Graphcore IPUs) push efficiency further by eliminating general-purpose overhead for specific workload patterns (matrix multiplication for deep learning).
**Algorithm-Level Efficiency**: **Communication-avoiding algorithms** reduce network energy by performing redundant computation (cheap, local) to avoid communication (expensive, remote). **Mixed-precision computing** uses FP16 or BF16 for bulk computation and FP64 only where needed — halving memory traffic and doubling compute throughput. **Approximate computing** trades precision for energy in applications that tolerate error (Monte Carlo simulations, neural network inference).
**Facility-Level Optimization**: Power Usage Effectiveness (PUE) = total facility power / IT equipment power. Best-in-class HPC facilities achieve PUE 1.05-1.15 (only 5-15% overhead for cooling and infrastructure). Techniques: **liquid cooling** (direct-to-chip water cooling eliminates fans and enables heat reuse for building heating), **free cooling** (using ambient air or water in cold climates), and **waste heat recovery** (using rejected heat for district heating — common in Scandinavian HPC facilities).
**Energy efficiency in HPC embodies the inescapable physics of computing — every floating-point operation requires energy to switch transistors and move data, and as system scale approaches the limits of practical power delivery and cooling, energy efficiency becomes the primary constraint on computational capability and the key differentiator between competitive and obsolete supercomputer designs.**