energy efficient computing
**Energy-Efficient Parallel Computing** is the **design and optimization of parallel systems and algorithms to minimize energy consumption (joules) and power draw (watts) while meeting performance targets**, driven by the end of Dennard scaling (power density no longer decreasing with transistor shrinking), rising electricity costs, thermal limits, and sustainability mandates for data centers.
Energy efficiency has become a first-class design metric alongside performance: modern supercomputers consume 20-40 MW (annual electricity cost $20-40M), data centers consume ~1-2% of global electricity, and the rapid growth of AI training is accelerating power demand. The Green500 list ranks supercomputers by GFLOPS/watt alongside the Top500 performance ranking.
**Energy Efficiency Hierarchy**:
| Level | Technique | Impact |
|-------|----------|--------|
| **Algorithm** | Reduce total operations, communication | 2-100x |
| **Architecture** | Specialized accelerators, near-memory compute | 10-100x |
| **System** | DVFS, power gating, heterogeneity | 2-10x |
| **Cooling** | Liquid cooling, free cooling, heat reuse | 1.2-2x (PUE) |
| **Software** | Power-aware scheduling, race-to-idle | 1.2-2x |
**DVFS (Dynamic Voltage and Frequency Scaling)**: Power scales as CV^2f. Reducing voltage by 20% reduces dynamic power by 36% with proportional frequency reduction. Optimal DVFS strategy depends on workload: **compute-bound** tasks benefit from full speed (race-to-idle); **memory-bound** tasks benefit from reduced frequency (memory latency dominates, slower clocks save power without proportional performance loss).
**Power-Aware Job Scheduling**: Allocate jobs to minimize energy: **consolidation** — pack jobs onto fewer nodes, power down idle nodes; **topology-aware** — place communicating tasks on nearby nodes to reduce network energy; **heterogeneity-aware** — run each task phase on the most energy-efficient processor (e.g., memory-bound phases on efficient cores, compute-bound on powerful cores); **thermal-aware** — distribute heat across racks to avoid cooling hotspots.
**Algorithmic Energy Efficiency**: The most impactful improvements: **communication-avoiding algorithms** — reduce data movement (moving 64 bits costs 100-1000x more energy than a floating-point operation); **mixed-precision** — use FP16/BF16 for AI training (2-4x more efficient than FP32 with minimal accuracy loss); **sparsity exploitation** — skip zero computations in sparse models/matrices; **approximate computing** — tolerate small errors for large energy savings in error-tolerant applications.
**Data Center PUE (Power Usage Effectiveness)**: PUE = total facility power / IT equipment power. Best modern data centers achieve PUE 1.05-1.10 using: **direct liquid cooling** (water or dielectric fluid to CPUs/GPUs, eliminating air conditioning), **hot aisle containment** (separating hot and cold air streams), **free cooling** (using outside air or water when climate permits), **waste heat reuse** (redirecting data center heat to district heating or greenhouses), and **power distribution optimization** (reduce conversion losses with 48V to point-of-load architecture).
**GPU/Accelerator Efficiency**: Specialized hardware delivers 10-100x better GFLOPS/watt than general-purpose CPUs for specific workloads: Google TPU v4 achieves ~275 TFLOPS at ~175W for BF16; NVIDIA H100 delivers ~990 TFLOPS at ~700W for FP16 Tensor Core; and emerging analog/photonic accelerators promise another 10-100x improvement for AI inference.
**Energy-efficient computing has shifted from an environmental concern to an engineering imperative — power and cooling are now the binding constraints on computational capability, making energy optimization essential for every level of the technology stack from algorithms to architecture to infrastructure.**