esd protection

**ESD Protection** — circuits and structures designed to safely dissipate electrostatic discharge events (up to several kilovolts) that would otherwise destroy the thin gate oxides and junctions in modern ICs. **The Threat** - Human body discharge: ~2-4 kV, ~1A peak current for ~100ns - Gate oxide breakdown: ~5-10V (modern thin oxides) - Without protection: A single static discharge destroys the chip **ESD Models** - **HBM (Human Body Model)**: Simulates human touching a pin. 2kV, 100ns pulse - **CDM (Charged Device Model)**: Chip itself is charged, then discharged. <1ns, very high current. Hardest to protect against - **MM (Machine Model)**: Lower voltage but higher current than HBM **Protection Circuits** - **Diode clamps**: Forward-biased diodes to VDD/VSS rails. Simple, effective - **GGNMOS (Grounded Gate NMOS)**: Triggers in snapback mode — low on-resistance, handles high current - **SCR (Silicon Controlled Rectifier)**: Highest ESD robustness per area. Used when space is critical - **Power clamps**: RC-triggered NMOS between VDD and VSS to handle ESD on power pins **Design Challenges** - Must clamp fast enough (<1ns for CDM) - Must not interfere with normal operation (parasitic capacitance affects high-speed I/O) - Must handle ESD on every pin including power **ESD protection** is mandatory on every I/O pin — a chip without it would fail in any real-world handling environment.