What Is an Etch Polysilicon Process Oes Endpoint Algorithm

An etch polysilicon process Optical Emission Spectroscopy endpoint algorithm (etch polysilicon process OES endpoint algorithm) is a real-time multi-spectral signal processing and statistical classification engine engineered to govern the critical transition from bulk gate etching to atomic-scale dielectric landing. During the patterning of polycrystalline silicon (poly-Si) or amorphous silicon dummy gates in sub-10nm CMOS and 3D NAND word lines, the etch tool uses high-density $HBr/Cl_2/O_2/CF_4$ inductively coupled plasmas. The primary challenge is that the polysilicon gate must clear completely across a 300mm wafer with zero residual conductive stringers, while preserving an underlying gate dielectric or pad oxide ($SiO_2/HfO_2$) that is often only 1.0 nm to 1.5 nm thick. An OES endpoint algorithm continuously tracks the optical emission signatures of volatile silicon halide reaction byproducts (such as $Si^*$ at 288.2 nm and $SiBr^*$ at 413.5 nm) alongside unreacted halogen etchants ($Br^*$ at 700.5 nm and $Cl^*$ at 725.6 nm). By applying multi-line ratioing, noise-adaptive Savitzky-Golay filtering, and second-derivative zero-crossing detection, the algorithm identifies the exact onset of wafer-scale clearing, commanding the tool to transition into an ultra-high selectivity over-etch within tens of milliseconds. At a high level, how a polysilicon OES endpoint algorithm operates during gate patterning looks like this:

A few principles are essential for understanding how polysilicon OES endpoint algorithms operate, why single-wavelength intensity thresholds fail in high-volume manufacturing, and how multi-line stoichiometry ratios guarantee sub-nanometer gate oxide retention:

Spectroscopic emission signatures in $HBr/Cl_2/O_2$ poly etch chemistry. In modern gate patterning, polysilicon is etched using a delicate balance of chemical halogens and passivating oxidizers:

Trace oxygen ($O_2$) is introduced to form a thin silicon oxy-halide passivating film ($SiO_xBr_y$) on vertical sidewalls, ensuring straight gate profiles. When energetic plasma electrons impact these molecules, they generate distinct emission lines:
- *Silicon Reaction Byproducts (Collapse at Endpoint):* Neutral silicon atomic line $Si^*$ emits intensely at 288.16 nm ($3p^2\,^1D_2 \rightarrow 3p4s\,^1P_1^\circ$). Silicon mono-bromide ($SiBr^*$) emits molecular bandheads between 410 nm and 425 nm (peaking at 413.5 nm). Silicon mono-chloride ($SiCl^*$) emits around 281.4 nm.
- *Unconsumed Halogen Reactants (Surge at Endpoint):* Atomic bromine ($Br^*$) lines emit strongly in the near-infrared at 700.5 nm, 751.3 nm, and 827.2 nm. Atomic chlorine ($Cl^*$) emits at 725.6 nm and 837.6 nm. As polysilicon clears across the wafer, reactant consumption drops abruptly, causing etchant emission to spike sharply.

The dual-line ratio metric cancels chamber seasoning drift. During long production runs, chamber wall liners (typically anodized aluminum or yttria, $Y_2O_3$) accumulate silicon oxy-bromide and carbonaceous polymer deposits. This seasoning layer slowly modifies chamber impedance, plasma electron density, and optical viewport transmission. If an algorithm monitored absolute $Si^*$ intensity alone ($I(288.2\text{ nm}) < \text{Threshold}$), wall conditioning drift would trigger false endpoints. By dividing the decaying byproduct line by the surging halogen reactant line:

the numerator falls while the denominator rises, creating an exponential signal collapse with a signal-to-noise ratio ($SNR > 28\text{ dB}$) that is mathematically immune to chamber wall seasoning and optical window clouding.

Second-derivative zero-crossing ($d^2R/dt^2 = 0$) and persistence timer. Because wafer-to-wafer polysilicon thickness varies across incoming chemical vapor deposition (CVD) lots, the exact time of clearing shifts by several seconds. When the ratio cliff begins:
1. *Inflection Point Recognition:* The first derivative $dR/dt$ plunges to a steep negative minimum. The second derivative $d^2R/dt^2$ passes through zero at the exact inflection point where 50% of the wafer area has cleared:

2. *Persistence Verification:* A digital persistence counter confirms that the zero-crossing condition is maintained for at least 150 ms to 300 ms, rejecting instantaneous RF matching coil flickers.
3. *Soft-Landing Trigger:* The cluster controller receives the trigger interrupt and commands an instantaneous recipe step change: shutting off aggressive $Cl_2$, reducing RF bias power from 150 W to 30 W, and increasing $O_2$ flow. In this low-bias $HBr/O_2$ regime, the selectivity of silicon over $SiO_2$ increases from 15:1 to $>150:1$, cleanly etching residual polysilicon stringers from dense pattern corners without punching through the fragile gate dielectric.

Low open-area multivariate PCA for advanced fin and nanosheet gates. When patterning FinFET dummy gates or gate-all-around (GAA) nanosheets, pattern open area drops to below 2%, meaning only a fraction of the wafer generates silicon emission. Under such low-signal regimes, single-wavelength OES exhibits low signal-to-noise. Modern etch tools deploy multivariate Principal Component Analysis (PCA) algorithms:

By analyzing hundreds of wavelengths simultaneously, the PCA algorithm extracts the dominant collective variance vector ($PC_1$), cleanly revealing the gate clearing inflection even when individual spectral lines are visually buried in background continuum noise.

Read a polysilicon etch process OES endpoint algorithm through a *wafer-clearing-referee* lens: it monitors the atomic halogen conversation inside the chamber to catch the precise millisecond when the bulk gate material vanishes across all 300 millimeters of the wafer, enabling an instantaneous chemical downshift that preserves atomic gate dielectrics across millions of transistors.