Confront the Experimental Mos Speed Deficit Against Bipolar Switching Speed

# Confront the Experimental MOS Speed Deficit Against Bipolar Switching Speed

## 1. Why Early PMOS Could Not Yet Match Bipolar Switching Speed at Any Reasonable Voltage

Measured directly against the delay figures Step 11 already established for RTL and DTL, early experimental PMOS gates ran distinctly slower, limited by the combination of low hole mobility (Step 5), relatively thick early gate oxides (which keep gate capacitance, and therefore switching time, high), and channel resistance that had not yet been reduced by the geometry scaling later decades would apply — a genuine, unhidden speed deficit, not a minor caveat. The delay-limiting chain, stated explicitly:

## 2. Real Diagram: Delay Comparison, Updated With This Step's Own Measurement

Placing early PMOS's own measured delay alongside Step 11's RTL and DTL figures on one consistent axis shows the gap plainly: not a close contest decided on secondary factors, but a clear, multi-factor speed deficit that experimental MOS of this era carried honestly, and that would only close in later decades through geometry scaling and the eventual switch to the faster electron-mobility NMOS once oxide quality allowed it.

## 3. Delay Comparison, Updated With This Step's Own Measurement

This series does not need to soften this deficit to make experimental MOS's story interesting — its real contribution in this era was density and static power, demonstrated in Steps 15 and 16, not raw switching speed, and treating that honestly is more useful to a reader than a tidier but inaccurate narrative.